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company confidential ? 1 data sheet ? 2011 by atheros communications, inc. all rights reserved. athe ros?, atheros driven?, align?, atheros xr?, driving the wireles s future?, intellon?, no new wires?, orion? , plc4trucks?, powerpacket?, spread spectrum carrier?, ss c?, rocm?, super a/g?, super g? , super n?, the air is cleaner at 5-ghz?, total 802.11?, u- nav?, wake on wireless?, wireless future. unleashed now.?, and xspan?, are registered by atheros communications, inc. atheros s st?, signal-sustain technology?, ethos?, install n go?, ique?, rocm?, amp?, simpli-fi?, there is here?, u-map?, u-tag?, and 5-up? are trademarks of atheros com munications, inc. the atheros logo is a registered trademark of atheros communications, inc. all other trademarks are the property of their respectiv e holders. subject to change without notice. august 2011 version 1.1 AR8031 integrated 10/100/1000 mbps ethernet transceiver general description the AR8031 is part of the arctic family of devices ? which includes the AR8031, ar8033, and ar8035. the AR8031 is atheros? 4 th generation, single port , 10/100/1000 mbps, tri- speed ethernet phy. it supports both rgmii and sgmii interfaces to the mac. the AR8031 provides a low power, low bom (bill of materials) cost solution for comprehensive applications including enterprise, carrier and home networks such as cpe, home gateway, enterprise switch, carrier switch/router, mobile base station and base station controller, optical module and media converter, industry automation and measurement. the AR8031 integrates atheros green ethos ? power saving technologies and significantly saves power not only during the work time, but also overtime. atheros green ethos ? power savings include ultra-low power in cable unplugged mode or port power down mode, and automatic optimized power saving based on cable length. the AR8031 also supports ieee 802.3az eee standard (energy efficient ethernet) and atheros proprietary smarteee. smarteee allows legacy mac/soc devices without 802.3az support to function as a complete 802.3az system. further, the AR8031 supports wake-on-lan (wol) feature to be able to help manage and regulate total system power requirements. the AR8031 embeds cdt (cable diagnostics test) technology on-chip which allows customers to measure cable length, detect the cable status, and identify remote and local phy malfunctions, bad or marginal patch cord segments or connectors. some of the possible problems that can be detected include opens, shorts, cable impedance mismatch, bad connectors, termination mismatch, and a bad transformer. the AR8031 requires only a single, 3.3v power supply. on-chip regulators provide all the other required voltages. it integrates the termination r/c circuitry on both the mac interfaces (rgmii/sgmii) and the serial resistors for the line side. the AR8031 device also incorporates a 1.25 ghz serdes. this interface can be connected directly to a fiber-optic transceiver for 1000 base-x /100 base-fx mode or to mac device for sgmii interface. the AR8031 supports both 1588v2 and synchronous ethernet to offer a complete time synchronization solution to meet the next generation network requirements. the key new features supported by the device are: n clock synchronization between slave and grandmaster by the exchange of ptp packets. supports ieee 1588v2 by offering a 1588 paket parser, accurate time-stamping and insertion to support both one-step and two-step clock modes n supports both ieee 1588v2 and synchronous ethernet by offering recovered clock output from data on the network-line side. the AR8031 supports ieee 802.3az energy efficient ethernet (eee) standard. the key features supported by the device are: n 10 base-te phy uses reduced transmit amplitude. n 100 base-tx and 1000 base-t use low power idle (lpi) mode to turn off unused analog and digital blocks to save power while data traffic is idle. features n 10/100/1000 base-t ieee 802.3 compliant n supports 1000 base-t pcs and auto- negotiation with next page support n supports rgmii and/or sgmii interfaces to mac devices n supports fiber and copper combo mode when mac interface works in rgmii mode n supports additional ieee 1000 base-x and 100 base-fx with integrated serdes n rgmii timing modes su pport internal delay and external delay on rx path free datasheet http:///
2 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 2 ? august 2011 company confidential n supports atheros green ethos ? power saving modes with internal automatic dsp power saving scheme n supports ieee 802.3az (energy efficient ethernet) n supports smarteee which allows mac/ soc devices withoug 802.3az support to function as the complete 802.3az system n supports wake-on-lan (wol) to detect magic packet and notify the sleeping system to wake up n fully integrated digital adaptive equalizers, echo cancellers, and near end crosstalk (next) cancellers n supports synchronous ethernet with selectable recovered clock output n robust cable discharge event (cde) protection of 6 kv n error-free operation over up to 140 meters of cat5 cable n automatic channel swap (acs) n automatic mdi/mdix crossover n automatic polarity correction n ieee 802.3u compliant auto-negotiation n jumbo frame support up to 10kb (full duplex) n multiple loopback modes for diagnostics n robust surge protection with 750 v/ differential mode and 4 kv/common mode n cable diagnostic test (cdt) n single power supply: 3.3v, optional for external regulator for core voltage n 6mm x 6mm, 48-pin qfn package n industry temperature (i-temp) option available. AR8031 functional block diagram dac waveshape filter echo canceller next canceller hybrid circut pga feed forward equalizer adc agc timing and phase recovery deskewer decision feedback equalizer symbol encoder symbol decoder auto- negotiation mii management registers dll trd[0:3] sgmii/ serdes pma pcs trellis decoder rgmii serial interface 1588v2 rgmii sync-e
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 3 ? company confidential august 2011 ? 3 revision history date revsion details revision 2010/11/15 first draft 0.1 2011/4/14 general description n overall update for revision from mpw to mass production n block diagram: add sync-e and 1588v2 block pin descriptions n rxd [3:0], rx_dv pin damping resistor 22ohm requirement is deleted. n rst pin type change from "ih" to "i,? mass production chip does not have internal weak pu n int, wol_int from "i/o active high" change to "d active low" need an external pu n power on strapping led_act from "1.1v/1.2v selection" to "phy address [2]". n led_act/led_link1000/led_link10_100 from internal weak "pd" change to internal weak "pu". functional descriptions n 2.2.4 mode definition adds wo rk mode"1011" combo mode. electrical characteristics n 3.1 absolute maximum rating: update cdm max n 3.2 recommeded operating condition: update tj max n 3.7 clock characteristics: update valu es in table 3-13 recommended crystal parameters n update table 3-11 mdio ac characteristic to add tmdelay row register n 4.2.29led control (0x18): upda te register bit definitions n 4.2.30 manual led override (0x19): new register topside marking n add topside marking illustration 1.0 2011/8/29 electrical characteristics n 3.2 recommended operation conditions: delete dvddl/avddl, ? ja ; add vddh_reg, ? jt , avddl/dvddl (industria l and commer cial); add thermal conditions n 3.6 change title from mdio dc charat eristics to mdio/m dc dc...; change v ih min value and v il max value n 3.7 table 3-14: change jitter pk-pk max value to 100 n 3.11 digital pin design guide (new) registers n 4.2.3 status register ? copper page, ch ange bit[8] reset value to always 1 n 4.3.4 hib control and auto-neg test register: change bit[12], [6:5] to reserved n 4.3.5 external loopback sele ction, change bit[0] to r/w n 4.3.7 power saving control (new) n 4.4.75 sgmii control register 2 (new) n 4.4.76 sgmii control register 3(new) n 4.4.78 1588 rtc clock select register (new) 1.1
4 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 4 ? august 2011 company confidential
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 5 ? company confidential august 2011 ? 5 table of contents general description ........................................ 1 features ............................................................ 1 AR8031 functional block diagram .............. 2 revision history ............................................. 3 table of contents ............................................ 5 1 pin descriptions ............................ 9 1.1 power-on strapping pins ...................... 13 1.1.1 mode definition .......................... 14 2 functional description ............... 15 2.2 modes of operation ............................... 16 2.2.1 operation mode, copper .......... 16 2.2.2 operation mode, fiber ............... 16 2.2.3 operation mode , media converter 17 2.2.4 operation mode, auto-media detect (combo) ........................... 17 2.3 transmit functions ................................ 18 2.4 receive functions .................................. 18 2.4.1 decoder modes ........................... 18 2.4.2 analog to digital converter ...... 18 2.4.3 echo canceller ............................. 18 2.4.4 next canceller .......................... 18 2.4.5 baseline wander canceller ....... 18 2.4.6 digital adaptive equalizer ....... 18 2.4.7 auto-negotiation ........................ 19 2.4.8 smartspeed function ................. 19 2.4.9 automatic mdi/mdix crossover 19 2.4.10 polarity correction ..................... 19 2.5 loopback modes .................................... 19 2.5.1 digital loopback ......................... 19 2.5.2 external cable loopback ........... 19 2.5.3 remote phy loopback .............. 20 2.6 cable diagnostic test ............................ 20 2.7 fiber mode support .............................. 20 2.7.1 ieee 802.3 remote fault indication support ......................................... 20 2.7.2 fault propagation ....................... 21 2.8 led interface .......................................... 21 2.9 power supplies ....................................... 22 2.10 management interface .......................... 24 2.11 timing sychronization ......................... 26 2.11.1 synchronous ethernet ? physical layer timing synchronization . 29 2.12 atheros green ethostm ...................... 30 2.12.1 low power modes ..................... 30 2.12.2 shorter cable power mode ....... 30 2.12.3 hibernation mode ...................... 30 2.13 ieee 802.3az and energy efficient ethernet 30 2.14 ieee 802.3az energy efficient ethernet 30 2.14.1 ieee 802.3az lpi mode .............. 30 2.14.2 atheros smarteee ...................... 31 2.15 wake on lan (wol) .......................... 32 3 electrical characteristics ............33 3.1 absolute maximum ratings ................ 33 3.2 recommended operating conditions 33 3.3 rgmii characteristics ........................... 34 3.4 serdes and sgmii ch aracteristics ...... 37 3.5 mdio timing ......................................... 39 3.6 mdio/mdc dc characteristic .......... 39 3.7 clock characteristics ............................. 40 3.8 power pin current consumption ....... 41 3.9 typical power consumption parameters 41 3.10 power-on sequence, reset and clock 44 3.10.1 power-on sequence .................... 44 3.10.2 reset and clock timing ............. 44 3.11 digital pin design guide ..................... 44 4 register descriptions ..................47 4.1 register summary ................................. 47 4.2 mii registers .......................................... 47 4.2.1 control register ? copper page 49 4.2.2 control ? fiber page ................. 50 4.2.3 status register ? copper page 51 4.2.4 status register ? fiber page .... 53 4.2.5 phy identifier ............................. 54 4.2.6 phy identifier2 ........................... 55 4.2.7 auto-negotiation advertisement register ? copper page ........... 55 4.2.8 auto-negotiation advertisement register ? fiber page ................ 57 4.2.9 link partner ability register ?
6 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 6 ? august 2011 company confidential copper page ................................ 58 4.2.10 link partner ability register ? fiber page .................................... 59 4.2.11 auto-negotiation expansion register ? copper page ............ 60 4.2.12 auto-negotiation expansion register ? fiber page ................ 61 4.2.13 next page transmit register ? copper page ................................ 62 4.2.14 next page transmit register ? fiber page for 1000 base-x, sgmii 62 4.2.15 link partner next page register ? copper page ................................ 63 4.2.16 link partner next page register ? fiber page for 1000 base-x, sgmii 64 4.2.17 1000 base-t control register .. 64 4.2.18 1000 base-t status register ..... 66 4.2.19 mmd access control register . 67 4.2.20 mmd access address data register ......................................... 67 4.2.21 extended status register ........... 68 4.2.22 function control register ......... 68 4.2.23 phy-specific status register ? copper page ................................ 69 4.2.24 phy-specific status register ? fiber page .................................... 71 4.2.25 interrupt enable register .......... 72 4.2.26 interrupt status register ............ 73 4.2.27 smart speed register ................. 75 4.2.28 cable diagnostic tester (cdt) control register .......................... 76 4.2.29 led control ................................. 76 4.2.30 manual led override register 77 4.2.31 copper/fiber status register ... 78 4.2.32 cable diagnostic tester status register ......................................... 79 4.2.33 debug port (address offset set) 80 4.2.34 debug port2 (r/w port) ............ 80 4.2.35 chip configure register ............ 80 4.3 debug register descriptions ................ 83 4.3.1 analog test control ................... 83 4.3.2 serdes test and system mode control .......................................... 83 4.3.3 100base-tx test mode select .. 84 4.3.4 hib control an d auto-negotiation test register ................................ 85 4.3.5 external loopback selection ..... 85 4.3.6 test configuration for 10base-t 85 4.3.7 power saving control ................ 86 4.4 mdio interface register ....................... 87 4.4.1 pcs control ................................. 90 4.4.2 pcs status .................................... 90 4.4.3 eee capability ............................ 91 4.4.4 eee wake error counter .......... 91 4.4.5 p1588 control register .............. 92 4.4.6 p1588 rx_seqid ........................... 93 4.4.7 p1588 rx_sourceport_identity ... 93 4.4.8 p1588 rx_sourceport_identity ... 93 4.4.9 p1588 rx_sourceport_identity ... 93 4.4.10 p1588 rx_sourceport_identity ... 94 4.4.11 p1588 rx_sourceport_identity ... 94 4.4.12 p1588 rx_time_stamp ................. 94 4.4.13 p1588 rx_time_stamp ................. 94 4.4.14 p1588 rx_time_stamp ................. 95 4.4.15 p1588 rx_time_stamp ................. 95 4.4.16 p1588 rx_time_stamp ................. 95 4.4.17 p1588 rx_frac_nano ................... 95 4.4.18 p1588 rx_frac_nano ................... 96 4.4.19 p1588 tx_seqid ........................... 96 4.4.20 p1588 tx_sourceport_identity ... 96 4.4.21 p1588 tx_sourceport_identity ... 96 4.4.22 p1588 tx_sourceport_identity ... 97 4.4.23 p1588 tx_sourceport_identity ... 97 4.4.24 p1588 tx_sourceport_identity ... 97 4.4.25 p1588 tx_sourceport_identity ... 97 4.4.26 p1588 tx_timestamp ................... 98 4.4.27 p1588 tx_timestamp ................... 98 4.4.28 p1588 tx_time_stamp ................. 98 4.4.29 p1588 tx_time_stamp ................. 98 4.4.30 p1588 tx_time_stamp ................. 98 4.4.31 p1588 tx_frac_nano ................... 99 4.4.32 p1588 tx_frac_nano ..................... 99 4.4.33 p1588 orgin_correction_o ........ 99 4.4.34 p1588 orgin_correction_o ...... 100 4.4.35 p1588 orgin_correction_o ...... 100 4.4.36 p1588 orgin_correction_o ...... 100 4.4.37 p1588 ingress_ trig_time_o ...... 100 4.4.38 p1588 ingress_ trig_time_o ...... 100 4.4.39 p1588 ingress_ trig_time_o ...... 101
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 7 ? company confidential august 2011 ? 7 4.4.40 p1588 ingress_trig_time_o ...... 101 4.4.41 p1588 tx_latency_o .................. 101 4.4.42 p1588 inc_value_o .................... 102 4.4.43 p1588 inc_value_o .................... 102 4.4.44 p1588 nano_offset_o ................ 102 4.4.45 p1588 nano_offset_o ................ 102 4.4.46 p1588 sec_offset_o .................... 103 4.4.47 p1588 sec_offset_o .................... 103 4.4.48 p1588 sec_offset_o .................... 103 4.4.49 p1588 real_time_i ..................... 103 4.4.50 p1588 real_time_i ..................... 103 4.4.51 p1588 real_time_i ..................... 104 4.4.52 p1588 real_time_i ..................... 104 4.4.53 p1588 real_time_i ..................... 104 4.4.54 p1588 rtc_frac_nano_i ............. 104 4.4.55 p1588 rtc_frac_nano_i ............. 105 4.4.56 wake-on-lan internal address 1 105 4.4.57 wake-on-lan internal address 2 105 4.4.58 wake-on-lan internal address 3 105 4.4.59 rem_phy_lpbk .......................... 106 4.4.60 smarteee control 1 .................. 106 4.4.61 smarteee control 2 .................. 106 4.4.62 smarteee control 3 ................... 107 4.4.63 auto-negotiation control 1 .... 107 4.4.64 auto-negotiation status .......... 108 4.4.65 auto-negotiation xnp transmit . 108 4.4.66 auto-negotiation xnp transmit1 108 4.4.67 auto-negotiation xnp transmit2 109 4.4.68 auto-negotiation lp xnp ability 109 4.4.69 auto-negotiation lp xnp ability1 109 4.4.70 auto-negotiation lp xnp ability2 109 4.4.71 eee advertisement .................. 110 4.4.72 eee lp advertisement .............. 110 4.4.73 eee ability auto-negotiation result .......................................... 111 4.4.74 sgmii control register 1 ........ 111 4.4.75 sgmii control register 2 ........ 112 4.4.76 sgmii control register 3 ........ 112 4.4.77 clk_25m clock select ............ 112 4.4.78 1588 clock select ...................... 113 5 package dimensions .................115 6 ordering information ...............117 7 topside marking .......................117
8 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 8 ? august 2011 company confidential
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 9 ? company confidential august 2011 ? 9 1. pin descriptions this section contains a package pinout for the AR8031 qfn 48 pin and a listing of the signal descriptions (see figure 1-1 ). the following nomenclature is used for signal names: the following nomenclature is used for signal types described in table 1-1 : nc no connection to the internal die is made from this pin n at the end of the signal name, indicates active low signals p at the end of the signal name, indicates the positive side of a dif- ferential signal n at the end of the signal name indicates the negative side of a differential signal d open drain ia analog input signal i digital input signal ih input signals with weak internal pull-up, to prevent signals from floating when left open il input signals with weak internal pull-down, to prevent signals from floating when left open i/o a digital bidirectional signal oa an analog output signal o a digital output signal p a power or ground signal pd internal pull-down for input pu internal pull-up for input
10 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 10 ? august 2011 company confidential figure 1-1 shows the pinout diagram for AR8031. note: there is an exposed ground pad on the back side of the package. figure 1-1. AR8031 48-pin qfn pinout diagram (top view) 1 2 12 5 11 10 9 8 7 6 4 3 13 24 23 22 21 20 19 18 17 16 15 14 48 37 38 39 40 41 42 43 44 45 46 47 36 35 25 32 26 27 28 29 30 31 33 34 AR8031 top view exposed ground pad on bottom rstn lx vdd33 mdc int xtlo xtli avddl rbias vddh_reg trxp0 trxn0 avddl trxp1 trxn1 avdd33 trxp2 trxn2 avddl trxp3 trxn3 pps led_act led_link1000 gtx_clk tx_en rx_clk txd0 rx_dv rxd0 rxd1 vddio_reg rxd2 rxd3 led_link10_100 clk_25m mdio dvddl avddl sop son sd wol_int txd3 txd2 txd1 sin sip
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 11 ? company confidential august 2011 ? 11 table 1-1. signal to pin relation ships and descriptions symbol pin type description mdi trxp0, trxn0 11, 12 ia, oa media-depend ent interface 0, differential 100 ?? transmission line trxp1, trxn1 14, 15 ia, oa media-depend ent interface 1, differential 100 ?? transmission line trxp2, trxn2 17, 18 ia, oa media-depend ent interface 2, differential 100 ?? transmission line trxp3, trxn3 20, 21 ia, oa media-depend ent interface 3, differential 100 ?? transmission line rgmii gtx_clk 35 i, pd rgmii transmit clock, 125 mhz at 1000 mbps, 25 mhz at 100 mbps, and 2.5 mhz at 10 mb ps digital clock input rx_clk 33 i/o, pd rgmii receive clock, 125 mhz at 1000 mbps, 25 mhz at 100 mbps, and 2.5 mhz at 10 mbps digital clock output rx_dv 32 i/o, pd rgmii receive data valid rxd0 31 i/o, pd rgmii receive data 0 rxd1 30 i/o, pd rgmii receive data 1 rxd2 28 i/o, pd rgmii receive data 2 rxd3 27 i/o, pd rgmii receive data 3 tx_en 34 i, pd rgmii transmit enable txd0 36 i, pd rgmii transmit data 0 txd1 37 i, pd rgmii transmit data 1 txd2 38 i, pd rgmii transmit data 2 txd3 39 i, pd rgmii transmit data 3 sgmii/1000fx sip/sin 46, 45 ia 1.25 gbps tr ansmit differential inputs when this interface is used as a mac interface, the mac transmitter's positive output connects to sip and the mac transmitter's negative output connects to the sin. when this interface is used as a fiber interface, the fiber-optic transceiver's positive output conne cts to the sip and the fiber-optic transceiver's negative outp ut connects to the sin. sop/son 43, 42 oa 1.25 gbps receive differential outputs when this interface is used as a mac interface, the mac receiver's positive input connects to sop and the mac receiver's negative input connects to the son. when this interface is used as a fiber interface, the fiber-optic transceiver's positive input connect s to the sop and the fiber-optic transceiver's negative input connects to the son. sd 41 ia signal detect. 1.2 v voltage le vel. input signals must not exceed 1.4v. management interface and interrupt
12 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 12 ? august 2011 company confidential mdc 1 i, pu management data clock reference mdio 48 i/o, d, pu management data, 1.5 k ?? pull-up resistor to 3.3 v/ 2.5 v led led_act 23 i/o, pu parallel led output for 10/100/1000 base-t activity; active blinking led active based upon po wer-on strapping. if pulled up, active low; if pull ed-down, active high led_link1000 24 i/o, pu parallel led output fo r 1000 base-t link; led active based upon power-on strapping. if pulled up , active low; if pulled-down, active high led_link10_100 26 i/o, pu parallel led output for 10/100 base-t link. led active based upon power-on strapping of led_link1000. if led_link1000 is pulled up, this pin is active lo w; if led_link1000 is pulled-down, this pin is active high. high, external pu 10 mbps low, external pu 100 mbps system signal group/reference clk_25m 25 i/o synchronous ethernet recovered clock (25mhz, 50mhz, 62.5mhzor 125mhz) output, register configurable, or ieee 1588v2 reference 50 mhz- 125 mhz clock input. rstn 2 i system reset, active low. this pin requires an external pull-up resistor. xtli 7 ia crystal oscillator input; 27 pf capacitor to gnd. support external 25 mhz 1.2 v swing clock input through this pin. xtlo 6 oa crystal oscillator ou tput; 27 pf capacitor to gnd rbias 9 oa external 2.37 k ? 1% resistor to gnd to set bias current int 5 d, pd system interrupt output. th is pin is od-gate by default and requires external 10 k ? pull-up resistor, active low. wol_int 40 d, pd wake-on-lan interrupt output. this pin is od-gate by default and requires external 10 k ?? resistor pull-up, active with a low pulse of 32 link speed clock cycles. see ?wake on lan (wol)? on page 32 for details. power lx 3 oa power inductor pin. add an external 4.7 h/500 ma power inductor to this pin directly. vddh_reg 10 oa 2.5v regulator output. vddio_reg 29 oa regulator output for the rgmi i i/o voltage. it can be either 1.5v (default) or 1.8v. if 2.5v is in tended for the rgmii i/o, simply connect this pin with the 2.5v regulator output at pin 10. avddl 8, 13, 19, 44 p 1.1v analog input. connect to pin 47 through a bead table 1-1. signal to pin relationships and descriptions (continued) symbol pin type description
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 13 ? company confidential august 2011 ? 13 1.1 power-on strapping pins table 1-2 shows the pin-to-phy core power-on strapping relationship note: 0 = pull-down, 1 = pull-up. note: power-on strapping pins are latched during power-up reset or warm hardware reset. note: since the mac device input pins may be driven high or low during power-up or reset, phy power- on strapping status may be affected by the mac side. in this case an external 10 k pull-down or pull-up resistor is required to ensure stable status. dvddl 47 p 1.1v digital core power input. connect to power inductor directly and 10uf+0.1uf cerami c capacitors to gnd vdd33 4 p 3.3v input for switching regulator avdd33 16 p 3.3v input for phy, from vdd33 through a bead 1588v2 pins pps 22 o ieeev2 pulse per second output. 1 hz clock which is synchronous with internal rtc. table 1-1. signal to pin relationships and descriptions (continued) symbol pin type description table 1-2. power-on strapping pins phy pin phy core config signal description default internal weak pull-up/down rxd0 phyaddress0 led_act and rxd1-0 set the lower three bits of the physical address. the upper two bits of the physical address are set to the default, ?00?. 0 rxd1 phyaddress1 0 led_act phyaddress2 1 rx_dv mode[0] mode select bit 0 0 rxd2 mode[1] mode select bit 1 0 rx_clk mode[2] mode select bit 2 0 rxd3 mode[3] mode select bit 3 0 led_link1000 int select an external 10 k ? pull-down resistor is required 1
14 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 14 ? august 2011 company confidential 1.1.1 m ode definition table 1-3 shows the mode and its description. note: the 50 or 75 ?? is the single end output impedance. table 1-3. mode definition mode [3:0] description 0000 1000 base-t, rgmii 0001 1000 base-t, sgmii 0010 1000 base-x, rgmii, 50 ? 0011 1000 base-x, sgmii, 75 ? 0100 converter mode between 1000 base-x and 1000 base-t media, 50 ? 0101 converter mode between 1000 base-x and 1000 base-t media, 75 ? 0110 100 base-fx, rgmii, 50 ? 0111 converter mode between 100 base-fx and 100 base-tx media, 50 ? 1011 rgmii, copper fiber auto-detection 1110 100 base-fx, rgmii mode, 75 ? 1111 converter mode between 100 base-fx and 100 base-tx media, 75 ? others reserved
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 15 ? company confidential august 2011 ? 15 2. functional description the AR8031 is atheros's low cost gbe phy. it is a highly integrated analog front end (afe) and digital signal transceiver, providing high performance combined with substantial cost reduction. the AR8031 provides physical layer functions for half/full-duplex 10 base-te, 100 base-tx and 1000 base-t ethernet to transmit and receive high-speed data over standard category 5 (cat5) un-shielded twisted pair cable. the AR8031 10/100/1000 phy is fully 802.3ab compliant, and supports reduced gigabit media-independent interface (rgmii) to connect to a gigabit-capable mac. the AR8031 transceiver combines echo canceller, near end cross talk (next) canceller, feed-forward equalizer, joint viterbi, feedback equalizer, and timing recovery, to enhance signal performance in noisy environments. see ?AR8031 functional block diagram? on page 2 . table 2-1 shows a feature comparison across the AR8031, ar8033, and ar8035 family. note: AR8031, ar8033 are pin-to-pin compatible. ** 10 base-te, 100 base-tx, 1000 base-t are supported *** 100base-fx, and 1000base-x are supported table 2-1. AR8031, ar8033, and ar8035 comparison feature AR8031 ar8033 ar8035 rgmii yes yes yes sgmii yes yes cu ethernet ** yes yes yes eee (802.3az) yes yes yes wake-on-lan yes yes yes serdes/fiber *** yes yes 1588v2 yes sync-e yes yes packaging 48-pin 48-pin 40-pin
16 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 16 ? august 2011 company confidential 2.2 modes of operation 2.2.1 operation mode, copper the AR8031 operates in the followi ng modes, as illustrated below: figure 2-1 shows the copper operating mode for AR8031. sgmii is serial gmii interface which uses only 4 lines to connect with mac/soc. when copper-side link is established, sgmii will pass the copper-side link status (link, speed, duplex) to mac side for building the link. sgmii interface shar es the same serdes with fiber port. 2.2.2 operation mode, fiber figure 2-2 shows the fiber operating mode for AR8031. AR8031 supports both 1000 base-x and 100 base-fx modes which are configured by power-on strapping pins (see ?power-on strapping pins? on page 13 ) and by register 0x1f [3:0]. in fiber mode, the mdi+/-[3:0] can be left floating. figure 2-1. operating modes ? copper mac interface - rgmii - sgmii media types: - 10base-te - 100base-tx - 1000base-t soc or switch rj-45 AR8031 transformer figure 2-2. operating modes ? fiber mac interface - rgmii media types: - 100base-fx - 1000base-x fiber i/f - serial AR8031 fiber optics soc or switch
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 17 ? company confidential august 2011 ? 17 2.2.3 operation mode, media converter figure 2-3 shows the operating mode media converter for AR8031. AR8031 supports the following converter modes: n 100 base-fx fiber to 100 base-tx copper n 1000 base-x fiber to 1000 base-t copper converter mode can be configured by power- on strapping (see ?power-on strapping pins? on page 13 ). it can also be configured by register 0x1f [3:0]. the register configuration takes effect immediately. three leds are used to indicate fiber interface status. in converter mode, auto-negotiation is running independently on fiber and copper interfaces. link status can be checked from copper page and fiber page respectively. set 0x1f [15] to 1 to select copper page, set 0x 1f [15] to0 to select fiber page. offset addres s 0x0, 0x1, 0x4, 0x5, 0x6, 0x7, 0x8 and 0x11 refers to two register pages respectively. see ?register descriptions? chapter for details. when the fiber and copper interfaces link up to the same speed, packets can go through the phy. when 1000m converter mode (bx1000_conv) is enabled, the copper port can still link to 100m with a 100m link partner. but packets can not go through the phy. note: since the two interfaces implement auto- negotiation individually, controller is required to ensure the duplex and pause of two remote link partners are matched. in converter mode, the rgmii interface signal can be left floating. 2.2.4 operation mode, auto-media detect (combo) AR8031 supports auto-media detect feature which allows mac to detect active link partners and process data from copper or fiber interface according to the priority setting. the copper and fiber work modes can be enabled simultaneously by setting the mode bit to 1011 by power-on strapping pin or register 0x1f [3:0]. n no fiber or cable connection: both interfaces in power saving mode. n fiber connected: rgmii fiber mode. the phy uses external fiber signal detection from the fiber module along with the synchronization state machine to recognize a valid connection. n copper connected: rgmii copper mode. the phy recognizes copper connection by power transmitted over the copper line. n combo mode: when active link partners over both fiber and copper are detected, the phy operation mode is defined by priority setting. priority is configured at register 0x1f [10] (0 = copper; 1 = fiber). in auto media detect mode, fiber port can be configured to 1000 base-x or 100 base-fx by register 0x1f[8] (1 = 1000 base-x, default setting; 0 = 100 base-fx). figure 2-3. operating modes ? media converter media type: - 100base-tx - 1000base-t media type: - 100base-fx - 1000base-x transformer rj-45 fiber interface: serdes AR8031
18 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 18 ? august 2011 company confidential 2.3 transmit functions table 2-2 describes the transmit function encoder modes. 2.4 receive functions 2.4.1 decoder modes table 2-3 describes the receive function decoder modes. 2.4.2 analog to digital converter the AR8031 device employs an advanced high speed adc on each receive channel with high resolution, which results in better snr and lower error rates. 2.4.3 echo canceller a hybrid circuit is used to transmit and receive simultaneously on each pair. a signal reflects back as an echo if the transmitter is not perfectly matched to the line. other connector or cable imperfections, such as patch panel discontinuity and variations in cable impedance along the twisted pair cable, also result in drastic snr degradation on the receive signal. the AR8031 device implements a digital echo canceller to adjust for echo and is adaptive to compensate for the varied channel conditions. 2.4.4 next canceller the 1000 base-t physical layer uses all four pairs of wires to transmit data. because the four twisted pairs are bundled together, significant high frequency crosstalk occurs between adjacent pairs in the bundle. the AR8031 device uses three parallel next cancellers on each receive channel to cancel high frequency crosstalk. the AR8031 cancels next by subtracting an estimate of these signals from the equalizer output. 2.4.5 baseline wander canceller baseline wander results from ethernet links that ac-couple to the transceivers and from ac coupling that cannot maintain voltage levels for longer than a short time. as a result, transmitted pulses are di storted, resulting in erroneous sampled values for affected pulses. baseline wander is more problematic in the 1000 base-t environment than in 100 base- tx due to the dc baseline shift in the transmit and receive signals. the AR8031 device uses an advanced baseline wander cancellation circuit that continuously monitors and compensates for this effect, minimizi ng the impact of dc baseline shift on the overall error rate. 2.4.6 digital adaptive equalizer the digital adaptive equalizer removes inter- symbol interference at the receiver. the digital adaptive equalizer takes unequalized signals from adc output and uses a combination of feedforward equalizer (ffe) and decision table 2-2. transmit function encoder modes encoder mode description 1000 base-t in 1000 base-t mode, the AR8031 scrambles transmit data bytes from the mac interfaces to 9-bit symbols and encodes them into 4d five-level pam signals over the four pairs of cat5 cable. 100 base-tx in 100 base-tx mode, 4-bit data from the mii is 4b/5b serialized, scrambled, and encoded to a three-level mlt3 sequence transmitted by the pma. 10 base-te in 10 base-te mode, the AR8031 transmits and receives manchester-encoded data. table 2-3. receive function decoder modes decoder mode description 1000 base-t in 1000 base-t mode, the pma recovers the 4d pam signals after accounting for the cabling conditions such as skew among the four pairs, the pair swap order, and the polarity of the pairs. the resulting code group is decoded into 8-bit data values. data stream delimiters are translated appropriately and data is output to the mac interfaces. 100 base-tx in 100 base-tx mode, the receive data stream is recovered and descrambled to align to the symbol boundaries. the aligned data is then parallelized and 5b/ 4b decoded to 4-bit data. this output runs to the mii receive data pins after data stream delimiters have been translated. 10 base-te in 10 base-te mode, the recovered 10 base-te signal is decoded from manchester then aligned.
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 19 ? company confidential august 2011 ? 19 feedback equalizer (dfe) for the best- optimized signal-to- noise (snr) ratio. 2.4.7 auto-negotiation the AR8031 device supports 10/100/1000 base-t copper auto-negotiation in accordance with ieee 802.3 clauses 28 and 40. auto- negotiation provides a mechanism for transferring information between a pair of link partners to choose the best possible mode of operation in terms of speed, duplex modes, and master/slave preference. auto-negotiation is initiated upon any of the following scenarios: n power-up reset n hardware reset n software reset n auto-negotiation restart n transition from power-down to power-up n the link goes down if auto-negotiation is disabled, a 10 base-te or 100 base-tx can be manually selected using the ieee mii registers. note: smartspeed enable bit requires a software reset to take effect after writing (write register 0x0[15]). 2.4.8 smartspeed function the atheros smartspeed function is an enhanced feature of auto-negotiation that allows the AR8031 device to fall back in speed based on cabling conditions as well as operate over cat3 cabling (i n 10 base-t mode) or two-pair cat5 cabling (in 100 base-tx mode). by default, the smartspeed feature is enabled. refer to the register ?smart speed register? on page 75 , which describes how to set the parameters. set these register bits to control the smartspeed feature: n bit [5]: 1 = enables smartspeed (default) n bits [4:2]: sets the number of link attempts before adjusting n bit [1]: timer to determine the stable link condition note: smartspeed enable bit needs a software reset (write register 0x0[15] = 1?b1 to take effect after writing. 2.4.9 automatic mdi/mdix crossover during auto-negotiation, the AR8031 device automatically determines and sets the required mdi configuration, eliminating the need for external crossover cable. if the remote device also implements automatic mdi crossover, the crossover algorithm as described in ieee 802.3 clause 40.4.4 ensures that only one device performs the required crossover. 2.4.10 polarity correction if cabling has been incorrectly wired, the AR8031 automatically corrects polarity errors on the receive pairs in 1000 base-t, 1000base- tx, and 10 base-te modes. 2.5 loopback modes 2.5.1 digital loopback digital loopback provides the ability to loop transmitted data back to the receiver using digital circuitry in the AR8031 device. figure 2- 4 shows a block diagram of digital loopback. followings are the register settings for loopback mode selection: n 1000m loopback: register 0x0 = 0x4140 n 100m loopback: register 0x0 = 0x6100 n 10m loopback: register 0x0 = 0x4100 2.5.2 external cable loopback external cable loopback loops rgmii/sgmii tx to rgmii/sgmii rx through a complete digital and analog path and an external cable, thus testing all the digital data paths and all the analog circuits. figure 2-5 shows a block diagram of external cable loopback. figure 2-4. digital loopback figure 2-5. external cable loopback mac/ switch rgmii/ sgmii phy ? digital phy ? afe mac/ switch phy ? digital rj \ 45 phy ? afe rgmii /sgmii
20 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 20 ? august 2011 company confidential to configure external loopback: 1. plug in an external loopback cable (1-3/2-6/ 4-7/5-8). 2. set debug register bit 0xb[15] to 0 to disable hibernate (power saving) mode. 3. set debug register bit 0x11[0] to 1 to enable external loopback. 4. set register 0x0 to select loopback modes: ? 1000m loopback: register 0x0 = 0x8140 ? 100m loopback: register 0x0 = 0xa100 ? 10m loopback: register 0x0 = 0x8100 note: when cable is removed and then reconnected to 1000m mode, the register 0x0 must be configured again to 0x8140 to establish phy link. 2.5.3 remote phy loopback remote phy loopback connects the mdi receive path to the mdi transmit path, thus the remote link partner can detect the connectivity in the resulting loop. figure 2-6 shows a block diagram of external cable loopback. to enable remote phy loopback, set mmd3 register bit 0x805a[0] to 1. note: when remote loopback is enabled, packets from link partne r will still appear at rgmii interface. remote loopback is independent of phy auto-negotiation. 2.6 cable diagnostic test the cable diagnostic test (cdt) feature in the AR8031 device uses time domain reflectometry (tdr) to identify remote and local phy malfunctions, bad/marginal cable or patch cord segments, or connectors. some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, termination mismatch, and bad magnetics. the cdt can be performed when there is no link partner or when the link partner is auto-negotiating. to perform the cable diagnostic test: 1. set register bits 0x16[9:8] to select the mdi pair to be tested 2. set register bit 0x16 to 1 to enable cdt 3. check register bits 0x1c[9:8] for cable failure status. 4. check register bits 0x1c[7:0] for delta time. the distance between the falure point and phy is [delta time] * 0.824. 2.7 fiber mode support besides standard 10/100/1000 base-t copper port support, both AR8031 and AR8031 provide additional ieee 1000 base-x and 100 base-fx support in fiber applications through integrated serdes. both the AR8031 and the ar8033 can work in rgmii mode to fiber or 10/100/1000 base-t to fiber. besides 1000 base-x and 100 base-fx support, both devices will support ieee 802.3 remote fault indication and fault propagation in fiber application. 2.7.1 ieee 802.3 remote fault indication support remote fault allows stat ions on a fiber optic link to know when there is a problem on the link. without remote fault, a station can not detect a problem that affects only one fiber (transmit, for example). with remote fault, the loss of a receive signal (link) causes the transm itter to send a special pattern of data indicating that a fault has occurred. 84 '1's followed by a single '0' is sent three times, in-band, and is readily detectable by the remote station, but is constructed so as to not satisfy the 100base-x carrier sense criterion, so the message will not be interpreted as normal traffic. if the remote station has remote fault, the link is dropped. if the remote station does not have remote fault, the special data pattern is ignored. the AR8031 indicates whether or not a remote fault pattern has been received from the remote station using the "remote fault status bit". this "remote fault status bit" can be "propagated" (see below) to the copper links on both ends of a fiber link. in the event of a figure 2-6. remote phy loopback mac/ switch rgmii/ sgmii phy digital phy afe rj-45
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 21 ? company confidential august 2011 ? 21 detected fault, both ends of the link can be notified of the failure in this way. this is particularly useful given the distances fiber links are generally used over. 2.7.2 fault propagation the AR8031 supports fault propagation - this allows the fiber link fault to be propagated to the twisted-pair copper connections where the "link down" status can be easily and quickly detected. the following steps describe fault propagation (for both 100 base-fx and 1000 base-x): the AR8031 supports fault propagation - this allows the fiber link fault to be propagated to the twisted-pair copper connections where the "link down" status can be easily and quickly detected. the following steps describe fault propagation (for both 100 base-fx and 1000 base-x): n the twisted-pair transmit path will be off when the receive path of the fiber link has no signal detected or is link down. the two fiber media types are then handled as described below: n the media converter (in 100 base-fx mode) will transmit far-end fault message, on the tx pair, when the receive path of fiber has no signal detected or is link down. this alerts the media converter on the remote end of the link. n the transmit twisted-pair will then be switched off on the remote end of the link. n the media converter (in 1000 base-x mode) will restart auto-negotiation when the receive path of the fiber detects no signal or is link down. n auto-negotiation will carry remote fault indications from the transmit fiber and the local station will restart auto-negotiation when its' receive path has no detected signal or is link down. n the twisted-pair transmit path will be off when the receive path of a 1000 base-x learns of the fault from an an message. figure 2-7 shows the fiber fault mechanism. 2.8 led interface the led interface can either be controlled by the phy or controlled manually, independent of the state of the phy. the leds have three status to indicate oper ation speed, traffic mode, and link status. the leds can be programmed to different status functions from their default value. figure 2-8 and figure 2-9 shows the references designs for the led interface. figure 2-7. fiber fault propagation or re- auto-negotiation figure 2-8. reference design for led, active high rx tx tx rx off twisted- pair fiber twisted- pair fiber far-end-fault or re-auto negotiation rx tx tx off rx 10 ? k ? 510 470 ? pf AR8031 led_act
22 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 22 ? august 2011 company confidential the active status of led_act and led_link1000 depends on power-on strapping mode. when the interface is strapped high, the led interface are active low; when strapped low, active high. the active status of led_link10_100 depends on led_link1000 power-on strapping mode and thus led_link10_100 and led_link1000 use the same led reference design. note: on = active; off = inactive 2.9 power supplies the AR8031 device requires only one 3.3 v external power supply. internal power rails are 3.3 v, 2.5v, 1.1v and 1.8v/1.5v. AR8031 integrates a switch regulator to convert 3.3v to 1.1v with high efficiency for core power rail, thus external regulator is optional. two on-chip ldos are integrated to support 2.5v/1.5v/1.8v rgmii i/o voltages. AR8031 can also work at 2.5 v rgmii i/o voltage and 3.3 v mac rgmii interface. since the input can bear 3.3v logic signal, and the output logic voh and vol can satisfy the 3.3v lvcmos/ lvttl requirement. refer to ?electrical characteristics? for parameter details. figure 2-9. reference design for led, active low 510 ? 470 ? pf AR8031 led_act vddh_reg 3.3 ? v 10 ? k ? table 2-4. led status symbol 10m link 10m active 100m link 100m active 1000m link 1000m active led_link10_100 off off on on off off led_link1000 off off off off on on led_act on blink on blink on blink
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 23 ? company confidential august 2011 ? 23 figure 2-10 shows the reference design for 2.5v/3.3v rgmii voltage level: figure 2-10. reference design, 2.5 v/ 3.3 v rgmii i/o AR8031 2.5v/3.3v rgmii
24 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 24 ? august 2011 company confidential figure 2-11 shows the reference design for 1.5/1.8 v rgmii voltage level. 2.10 management interface AR8031 integrates an mdc/mdio management interface in compliance with ieee802.3u clause 22. mdc is input clock reference provided by the mac. mdio is the management data input/ output bi-directional signal that runs synchronously to mdc. mdio is an od-gate and requires an external 1.5k pull-up resistor. table 2-5 shows the structure of the management frame. figure 2-11. reference design, 1.5/1.8 v rgmii i/o AR8031 1.5/1.8v rgmii table 2-5. management frame fields pre st op phyad regad ta data idle read 1...1 01 10 aaaa a rrrrr z0 dddddddddddddddd z write 1...1 01 01 aaaa a rrrrr 10 dddddddddddddddd z
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 25 ? company confidential august 2011 ? 25 table 2-6. management interface field definitions field definition pre a sequence of 32 contiguous single logic bits on mdio with corresponding cycles on mdc to provide phy with a pattern to for synchronization. st start of frame op operation code. 10 = read transaction, 01 = write transaction phyad phy address. the 5-bit phy address is configured by power-on strapping. three address bits can be configured in AR8031, thus eight phys can be connected to a single management interface. the phys connected to the same bus has unique phy addresses. the first phy addres s bit transmitted and received is the msb of the address. regad register address. the 5-bit register address allows 32 registers to be addressed at each phy. the first register address bit transmitted and received is the msb of the address. ta 2-bit field to avoid contention during a read operation. in read operation, both mac and phy are at high-impedance state for the first bit time. the phy drives a zero during the second bit time of the turnaround. in write operation, the mac must drive 10. data 16-bit data from accessed register. msn is transmitted first. idle high-impedance without driving state of the mdio. at least one clocked idle state is required between frames.
26 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 26 ? august 2011 company confidential 2.11 timing sychronization ieee 1588v2 provides a mechanism to synchronize the clocks across an ethernet network by exchanging the ieee 1588v2 packets. the slave node can adjust the local clock based on the the timing information calculated from timestamps exchanged. figure 3-8 shows the top-level use of the AR8031 to build a typical 1588v2 system. the AR8031 provides all the key componets to support an ieee 1588v2 operation. the ieee 1588v2 real time clock (rtc) generates and provides time information to other modules and software, timing information includes time of day and pps. ieee 1588v2 control accepts control information from software via mdc/mdio, generates control signals to other modules, and provides status information to software. ieee1588v2 timestamp unit, packet detction and processing, generates timestamps for ieee 1588v2 event messages and interrupt signals when receiving or transmitting ieee 1588v2 messages. the AR8031 supports ordinary, boundary and transparent clock modes as defined in ieee 1588v2 figure 3-9 shows the top level diagram of AR8031?s ieee 1588v2 module. also the AR8031 supports time- stamps to be encapsulated into the 1588v2 packet as explained in the following figure.
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 27 ? company confidential august 2011 ? 27 figure 2-12 top level use of AR8031 in an ieee 1588v2 system. figure 2-13 shows the top level diagram of the AR8031?s ieee 1588v2 module. on the transmit side, the phy will monitor and parse the incoming packet from the top layer, upon the request of sending ieee 1588v2 packet, it will calculat e the accurate time of transmission onto the media and a timestamp accordingly. the AR8031 supports both one-step and two- step clock modes, as defined in ieee 1588v2. no matter where accurate time information is carried ? in the follow-up message (two-step clock mode) or in the single event message (one-step clock mode), th e AR8031 will support figure 2-12. top level use of AR8031 in an ieee 1588v2 system figure 2-13. top level diagram of the AR8031?s ieee 1588v2 module AR8031 rgmii/ sgmii smi controller mac hardware software os 1588v2 software pps local 25mhz 1588 ref. clock (optional) line side atheros solution 1588v2 module rtc ieee 1588 timestamp unit packet detection and processing ieee 1588 control ieee 1588 real time clock time of day pps mdc/mdio rgmii/sgmii 1588v2 module
28 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 28 ? august 2011 company confidential correction filed update and crc recalculation on the fly. on the receive side, the phy will monitor and parse the incoming packet from media, and will generate a timest amp upon the reception of ieee 1588v2 packets. the built-in parser is capable of detecting ieee 1588v2 on ethernet layer 2 (including untagged, one vlan tagged and two vlan tagged), or layer 3 ipv4/udp, and ipv6/udp (including pppoe and snap). the following ieee 1588v2 packets are used to exchange the timing message for the delay request-response mechanism: n sync n follow_up n delay_req n delay_resp messages for the peer delay are also supported: n pdelay_req n pdelay_resp n pdelay_resp_follow_up the received ieee 1588v2 packet along with the timestamp will be forwarded to an external cpu/mac for further processing via accelerated mdc/mdio interfaces (running up to 25mhz). the AR8031 also supports time-stamp encapsultion into the 1588v2 packet as explained in the following figure 3-10. figure 2-14. ptp timestamp. AR8031 provides a pulse per second output, which locks onto the 1588v2 clock time of the device. the AR8031 1588v2 logic allows multiple reference clock sources, including: n local 25mhz crystal (default) figure 2-15. ptp timestamp l2/l3/l4 header ptp message 0 or more pads crc l2/l3/l4 header ptp message 0 or more pads attached timestamps crc remove old crc re-calculate crc 1. event ptp message attach timestamp of itself. 2. general ptp message attach timestamp of associated event ptp message if existed.
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 29 ? company confidential august 2011 ? 29 n recovered clock from sychronous ethernet n dedicated, external 50mhz ~ 125mhz 1588v2 reference clock the AR8031 ieee 1588v2 module is under tx fifo, so the fifo does not affect time stamping giving improved accuracy. refer to figure 3-11 below. also, the ieee 1588v2 module can be bypassed by register settings. figure 2-16. block diagram of the AR8031 1588v2 module. 2.11.1 synchronous ethernet ? physical layer timing synchronization the AR8031 supports synchronous ethernet for 100base-tx and 1000base-t applications figure 2-17. block diagram of the a r8031?s ieee 1588v2 module pcs mi i swi tch 1588v2 module rx tx rx tx ieee 1588v2 tx fifo block diagram: ieee 1588v2 module rgmii/sgmii
30 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 30 ? august 2011 company confidential by offering one recovered clock from the network line-side. this recovered clock output is register configurable to 25mhz (default), 50mhz, 62.5mhz or 125mhz, to meet the itu- t recommendations g.8261/y.1361. the network node can use this recovered clock to replace local clock sources and drive the local system. therefore all distributed nodes the network will use the same network clock to support synchronus and timing sensitive services like t1/e1 service over ethernet. see table 4.4.77 on page 112 ?clock select for details. 2.12 atheros green ethos tm 2.12.1 low power modes the AR8031 device supports the software power-down low power mode. the standard ieee power-down mode is entered by setting the power_down bit (bit [11]) of the register ?control? on page 18 equal to one. in this mode, the AR8031 ignores all mac interface signals except the mdc/mdio. it does not respond to any activity on the cat 5 cable. the AR8031 cannot wake up on its own. it can only wake up by setting the power_down bit of the ?control? register to 0. . 2.12.2 shorter cable power mode the AR8031 can attain an additional 25% power savings when a cable length is detected that is <30m vs. standard power consumption for a 100m cat5 cable. 2.12.3 hibernation mode the AR8031 device supports hibernation mode. when the cable is unplugged, the AR8031 will enter hibernation mode after about 10 seconds. the power consumption in this mode is very low when compared to the normal mode of operation. when the cable is re-connected, the AR8031 wakes up and normal functioning is restored. 2.13 ieee 802.3az and energy efficient ethernet ieee 802.3az provides a mechanism to greatly save the power consumption between data packets burst. the link partners enter low power idle state by sending short refresh signals to maintain the link. there are two operating states, active state for normal data transfer, and low-power state between the data packet bursts. in the low-power state, phy shuts off most of the analog and digital blocks to reserve energy. due to the bursty traffic nature of ethernet, system will stay in low-power mode in the most of time, thus the power saving can be more than 90%. at the link start up, both link partners exchange information via auto neg to determine if both parties are capable of entering lpi mode. legacy ethernet products are supported, and this is made transparent to the user. 2.14 ieee 802.3az energy efficient ethernet ieee 802.3az provides a mechanism to greatly save the power consumption between data packets burst. the link partners enter low power idle state by sending short refresh signals to maintain the link. there are two operating states, active state for normal data transfer, and low-power state between the data packet bursts. in the low-power state, phy shuts off most of the analog and digital blocks to reserve energy. due to the bursty traffic nature of ethernet, system will stay in low-power mode in the most of time, thus the power saving can be more than 90%. at the link start up, both link partners exchange information via auto neg. to determine if both parties are capable of entering lpi mode. legacy ethernet products are supported, and this is made transparent to the user. 2.14.1 ieee 802.3az lpi mode AR8031 works in the following modes when 802.3 az feature is turned on: n active: the regular mode to transfer data n sleep: send special signal to inform remote link of entry into low-power state n quiet: no signal transmitted on media, most of the analog and digital blocks are turned off to reduce energy. n refresh: send periodically special training signal to maintain timing recovery and equalizer coefficients
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 31 ? company confidential august 2011 ? 31 n wake: send special wakup signal to remote link to inform of the entry back into active. the AR8031 supports both 100 base-tx eee and 1000 base-t eee. 100 base-tx eee allows asymmetrical operation, which allows each link partner to enter the lpi mode independent of the other partner. 1000 base-t eee requires symmetrical operation, which means that both link partners must enter the lpi mode simultaneously. figure 2-3 shows the 802.3az operating states for the AR8031. figure 2-4 shows the 802.3az operating power modes ? 802.3az for the AR8031. 2.14.2 atheros smarteee AR8031 smarteee, compatible with ieee802.3az standard, is designed to include legacy mac without eee capability into the power saving system. smarteee is enabled by default configuration on AR8031 after power- on or hardware reset. AR8031 smarteee detects egress data flow to see if any packets being transferred at a defined interval and enters eee mode if no packet is detected. if packets come in at eee mode, it takes 16.5 s (typical) for AR8031 wake up (as defined by ieee802.3az) and send out the data after the time configur ed in register. AR8031 provides 2048 x 20-bit buffer for caching egress data to ensure no packet loss. in smarteee mode, the rx side does not generate mdi lpi pattern, thus only normal figure 2-18. operating states ? 802.3az lpi mode figure 2-19. operating power modes ? 802.3az lpi mode active active td quiet quiet quiet low-power refresh refresh sleep wake ts tq tr tw existing state used for data transmission. data packets or ipg/idle symbols are transmitted new state used during periods of no data transmission to allow system power reduction between data packet bursts operating states
32 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 32 ? august 2011 company confidential packets and idle packets can appear on the rgmii interface. no tx lpi pattern is generate for macs without eee capability since lpi is generated inside phy according to smarteee mechanism. for macs with eee capability, smarteee control registers can be set to bypass smarteee function. note: wait time before entering eee mode is configured at registers mmd3 0x805c,0x805d[7:0]. note: wake-up time from eee mode to sending out data is configurable at register mmd3 0x805b. this setting is used for collaboration with link partner for customized purpose. 2.15 wake on lan (wol) originally wake-on-lan (wol) was an ethernet networking standard that allowed a computer to be turned on (or woken up) by a network message for adminstrator attention, etc. however as part of the latest industry trend towards energy savings, and lower power consumption, wol gets wide interest to be adopted across networking systems as a mechanism to help to manage and regulate the total power consumed by the network. the AR8031 supports wake on lan (wol): n able to enter the sleep/isolate state (phy?s all tx bus (including clock) are in high-z state, but phy can stil l receive packets) by isolate bit in mii register configuration n consumes less than 50mw in sleep/isolate mode. n supports automatic detection of a specific frame containing anywhere within its payload: 6 bytes of ones (resulting in hexadecimal ff ff ff ff ff ff), followed by sixteen repetitions of the target computer's AR8031 internal mac address (48-bit address written in mmd3 0x804a, 0x804b, 0x804c)and notification via dedicated hardware interrupt n two hardware pins can be used for triggering wol interrupt: ? active low signal through int pin. once the interrupt bit in register 0x12[0] is set to 1, AR8031 generates interrupt at the reception of wol packet. ? active with pulse width of 32 clock cycles through wol_int pin at the reception of wol packet. clock frequencies for different traffic rates are: 1000 mbps: 125 mhz; 100 mbps: 25 mhz; 10 mbps: 2.5 mhz n supports wake-up from the sleep state by register configuration
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 33 ? company confidential august 2011 ? 33 3. electrical characteristics 3.1 absolute maximum ratings table 3-1 summarizes the absolute maximum ratings and table 3-2 lists the recommended operating conditions fo r the AR8031. absolute maximum ratings are those values beyond which damage to the device can occur. functional operation un der these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended. 3.2 recommended operating conditions note: external regulators are optional for supplying avddl/dvddl. for industrial version, external avddl/dvddl inputs must be within the range of 1. 2 v 5%. for commercial version, external avddl/ dvddl inputs must be within the range of 1.1 v-5% and 1.2 v+5%. table 3-1. absolute maximum ratings symbol parameter max rating unit vdd33/avdd33 3.3v supply voltage 3.8 v avddl 1.1v analog supply voltage 1.6 v dvddl 1.1v digital core supply voltage 1.6 v t store storage temperature ?65 to 150 c hbm electrostatic discharge tolerance - human body model 2000 v mm machine model 200 v cdm charge device model 300 v table 3-2. recommended operating conditions symbol parameter min typ max unit vdd33/avdd33 3.3v supply voltage 3.15 3.3 3.45 v vddh_reg 2.5 v analog/digital 2.4 2.62 2.75 v avddl/dvddl 1.1 v analog/digital 1.04 1.1 1.17 v t ambient ambient temperature for normal operation ? commercial chip version AR8031 -al1a 0?70 ? c ambient temperature for normal operation ? industrial chip version AR8031 -al1b -40 ? 85 ? c t j junction temperature -40 ? 125 ? c ? jt thermal dissipation coefficient ? 4 ? ? c/w
34 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 34 ? august 2011 company confidential note: the following condition must be satisfied: t jmax > t cmax + ? jt p typical where: t jmax = maximum allowable junction temperature t cmax = maximum allowable case temperature ? jt = thermal dissipation coefficient p typical = typical power dissipation 3.3 rgmii characteristics table 3-3 shows the rgmii dc characteristics with 2.5/3.3v i/o supply. table 3-4 shows the rgmii dc characteristics with 1.8v i/o supply. table 3-5 shows the rgmii dc characteristics with 1.5v i/o supply. table 3-3. rgmii dc characteristics ? 2.5/3.3v i/o supply symbol parameter min max unit i ih input high current ? 15 ? a i il input low current ?15 ? ? a v ih input high voltage 1.7 3.5 v v il input low voltage ? 0.7 v v oh output high voltage 2.4 2.8 v v ol output low voltage gnd ? 0.3 0.4 v table 3-4. rgmii dc characteristics ? 1.8v i/o supply symbol parameter min max unit v ih input high voltage 1.4 ? v v il input low voltage ? 0.4 v v oh output high voltage 1.5 ? v v ol output low voltage ? 0.3 v table 3-5. rgmii dc characteristics ? 1.5 i/o supply symbol parameter min max unit v ih input high voltage 1.2 ? v v il input low voltage ? 0.3 v v oh output high voltage 1.3 ? v v ol output low voltage ? 0.2 v
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 35 ? company confidential august 2011 ? 35 figure 3-1 shows the rgmii ac timing diagram ? no internal delay. table 3-6 shows the rgmii ac characteristics. figure 3-1. rgmii ac timing diagram ? no internal delay rx_clk, gtx_clk txd[3:0], rxd[3:0] rx_dv, tx_en t skewr t skewt rx_clk, gtx_clk table 3-6. rgmii ac characteristics ? no internal delay symbol parameter min typ max unit t skewt data to clock output skew (at transmitter) -500 0 500 ps t skewr data to clock output skew (at receiver) 1 ? ? ns t cyc clock cycle duration 7.2 8.0 8.8 ns duty g duty cycle for gigabit 45 50 55 % duty t duty cycle for 10/100t 40 50 60 % t r /t f rise/fall time (20 - 80%) ? ? 0.75 ns
36 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 36 ? august 2011 company confidential figure 3-2 shows the rgmii ac timing diagram with internal delay added (default rgmii timing). table 3-7 shows the rgmii ac characteristics with delay added. figure 3-2. rgmii ac timing diagram ? with internal delay added (default) table 3-7. rgmii ac characteristics ? with internal delay added (default) symbol parameter min typ max unit tsetupt data to clock output setup (at transmitter ? integrated delay) 1.65 2.0 2.2 ns tholdt clock to data output hold (at transmitter ? integrated delay) 1.65 2.0 2.2 ns tsetupr data to clock input setup time (at receiver ? integrated delay) 1.0 2.0 ns tholdr data to clock input hold time (at receiver ? integrated delay) 1.0 2.0 ns
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 37 ? company confidential august 2011 ? 37 3.4 serdes and sgm ii characteristics table 3-8 shows the driver dc characteristics. note: output differential voltage can be configured by register mmd7 0x8011 [15:13] table 3-8. driver dc characteristics symbol parameter min typical max unit vo h output voltage high 950 1050 mv vo l output voltage low 500 650 mv vr ing output ringing 10 % |vod| output differential voltage programmable #note 1 300 (default) mv vo s output offset voltage 750 800 850 mv ro output impedance (single ended) 50ohm termination 40 50 60 ohm output impedance (single ended) 75ohm termination 60 75 90 ohm delta ro mismatch in a pair 10 % delta v od change in v od between "0" and "1" 25 mv delta vos change in v os between "0" and "1" 25 mv isa,isb output current on short to gnd 40 ma isab output current when a, b are shorted 12 ma ixa,ixb power off leakage current 10 ma
38 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 38 ? august 2011 company confidential table 3-9 shows the receiver dc characteristics table 3-10 shows the driver ac characteristics. note: skew measured at 50% of the transition. table 3-9. receiver dc characteristics symbol parameter min typical max unit vio internal offset voltage 730 825 930 mv vih input single voltage high 1050 1150 mv vil input single voltage low 500 600 mv vidth input differential threshold -50 +50 mv vhyst input differential hysteresis 25 mv rin receiver differential input impedance 50ohm termination 80 100 120 ohm receiver differential input impedance 75ohm termination 120 150 180 ohm table 3-10. driver ac characteristics symbol parameter min max unit tfall vod fall time (20%-80%) 100 200 psec trise vo d r i s e t i m e (20%-80%) 100 200 psec tskew1 skew between two members of a differential pair 20 psec
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 39 ? company confidential august 2011 ? 39 3.5 mdio timing figure 3-3 shows the mdio ac timing diagram. 3.6 mdio/mdc dc characteristic figure 3-3. mdio ac timing diagram table 3-11. mdio ac characteristic symbol parameter min typ max unit tmdc mdc period 40 ns tmdcl mdc low period 16 ns tmdch mdc high period 16 ns tmdsu mdio to mdc rising setup time 10 ns tmdhold mdio to mdc ri sing hold time 10 ns tmdelay mdc to mdio output delay 10 30 ns table 3-12. mdio/mdc dc characteristic symbol parameter min max unit v oh output high voltage 2.4 ? v v ol output low voltage ? 0.4 v v ih input high voltage 1.7 ? v v il input low voltage ? 0.7 v i ih input high current ? 0.4 ma i il input low current -0.4 ? ma
40 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 40 ? august 2011 company confidential 3.7 clock characteristics AR8031 supports both crystal and external clock input as reference. the basic principle for selecting crystal and load capacitance is to make the oscillation stable at 25 mhz 50 ppm. crystal with 25 mhz 30 ppm frequency tolerance is preferred with two 27 pf npo ceramic capacitors. the capacitors can be changed according to actual crystal selection and board level test results under full application temperature and voltage ranges. figure 3-4. external crystal 1 2 3 27 pf 27 pf xtli xtlo AR8031 25 mhz table 3-13. recommended crystal parameters symbol parameter min typ max unit ff crystal fundamental frequency 25 mhz fs frequency stability over operating temperature @ 0?70 c ?30ppm +30ppm mhz ft frequency tolerance @ 25 c ?30ppm +30ppm mhz fo oscillation frequency ?50ppm +50ppm mhz cs shunt capacitance 7 pf cl load capacitance 15 pf vo i/o voltage level (for drive level evaluation) 1.2 v dl drive level 300 w esr equivalent series resistance 30 50 ? table 3-14. external clock input characteristic symbol parameter min typ max unit t_xi_per xi clock period 40.0 - 50ppm 40.0 40.0 + 50ppm ns t_xi_hi xi clock high 14 20.0 ns t_xi_lo xi clock low 14 20.0 ns t_xi_rise xi clock rise time, vil (max) to vih (min) 4ns t_xi_fall xi clock fall time, vil (max) to vih (min) 4ns v_ih_xi the xi input high level 0.8 1.2 1.5 v v_il_xi the xi input low level voltage - 0.3 0 0.15 v
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 41 ? company confidential august 2011 ? 41 clk_25m can be configured as the 1588 reference clock input by setting register mmd7 0x8017[11] =1'b1 to select external 1588v2 clock input as reference and the pin works as an input. table 3-15. clk_25m input characteristics as the 1588v2 reference clock 3.8 power pin current consumption table 3-16 shows the current consumption for the power pins. 3.9 typical power consumption parameters c in load capacitance 1 2 pf jitter rms period broadband rms jitter 15 ps jitter pk-pk period broadband peak to peak jitter 100 ps table 3-14. external clock input characteristic clk_25m 1588v2 input min typ max unit frequency -50ppm 50~125 +50ppm mhz input high voltage 2 2.8 v input low voltage gnd-0.3 0.8 v cin load capacitance 1 2 pf jitter (rms) 15 ps jitter (pk-pk) 200 ps table 3-16. power pin consumption symbol voltage range current (max) avddl 1.1v 5% 50.8 ma dvddl 1.1v 5% 113.7 ma avdd33 3.3v 10% 63.8 ma vddio_reg connect vddh_reg 2.5v 20.9 ma
42 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 42 ? august 2011 company confidential the following conditions apply to the typical characteristics unless otherwise specified: vcc = 3.3v (1.1v switching regulator integrated. 50mw rgmii power included). table 3-17. total system power symbol condition total current (ma) led consumption (ma) total power consumption w/o led (mw) p ldps link down, power saving mode 3 0 9.9 p pwd power down mode 7 0 23.1 rgmii + copper mode p 1000f 1000 base full duplex 120 2.7 396 p 1000idle 1000 base idle 105 4 346.5 p 100f 100 base full duplex 30 3.5 99 p 100idle 100 base idle 29 4 95.7 p 10f 10 base-te full duplex 25 1 82.5 p 10idle 10 base-te idle 5 1.5 16.5 802.az enabled p ldps 1000m idle 18.5 4 61.1 p ldps 100m idle 16.4 4 54.1 atheros proprietary green ethos ? power savings per cable length p 1000f 20m 1000 base full duplex 20m cable 90 2.7 297 p 1000f 20m 1000 base idle 20m cable 81 4 267.3 p 1000f 100m 1000 base full duplex 100m cable 120 2.7 396 p 1000f 100m 1000 base idle 100m cable 105 4 346.5 p 1000f 140m 1000 base full duplex 140m cable 135 2.7 445.5 p 1000f 140m 1000 base idle 140m cable 123 4 405.9 rgmii + fiber mode p 1000f 1000 base-x full duplex 27 2.7 89.1 p 1000idle 1000 base-x idle 25 4 82.6 p 100f 100 base-x full duplex 17 3.5 56 p 100idle 100 base-x idle 17 4 56 converter mode
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 43 ? company confidential august 2011 ? 43 note: please note power consumption test results are based on demo board. p 1000f 1000 base full duplex 143 2.7 471.9 p 1000idle 1000 base idle 134 4 442.2 p 100f 100 base full duplex 38 3.5 125.4 p 100idle 100 base idle 37 4 122.1 sgmii + copper mode p 1000f 1000 base full duplex 141 2.7 465.3 p 1000idle 1000 base idle 133 4 438.9 p 100f 100 base full duplex 39 4 128.7 p 100idle 100 base idle 38 4 125.4 802.3az enabled p 1000f 1000 base full duplex 27 4 89.1 p 100idle 100 base idle 23 4 75.9 table 3-17. total system power symbol condition total current (ma) led consumption (ma) total power consumption w/o led (mw)
44 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 44 ? august 2011 company confidential 3.10 power-on sequence, reset and clock 3.10.1 power-on sequence the AR8031 only needs a single 3.3v power supply input. the 1.1v core and 2.5v, 1.8v/ 1.5v voltages are generated by AR8031's internal regulators. so the AR8031?s power-on sequence to establish the power rails stability is met internally. 3.10.2 reset and clock timing the AR8031 hardware reset needs the clock to take effect. input clock including the crystal and external input clock should be stable for at least 1 ms before reset can be de-asserted. for chip reliability, an external clock must be input after the power-on sequence. figure 3-5 shows the reset timing diagram. note: when using crystal, clock is generated internally af ter the power is stable. in order to get reliable power-on-reset, it is recommended to keep asserting the reset low signal long enough (10 ms) to ensure the clock is stable and clock-to-res et (1 ms) requirement is satisfied. 3.11 digital pin design guide figure 3-5. reset timing diagram table 3-18. digital pin designs pin type pin description reset asserted re set de-asserted (normal working level) input txd[3:0] tx_en gtx_clk input, internal weak pd input, ba sed on rgmii i/o voltage level set i/o rxd[3:0] rx_dv rx_clk input, internal weak pd output, ba sed on rgmii i/o voltage level set i/o led_link1000 led_act led_link10_100 input, internal weak pu output, 2.5 v (vddh_reg)
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 45 ? company confidential august 2011 ? 45 note: when mdc/mdio/reset acts as an input, v ih min is 1.7 v, v il max is 0.7 v, thus the chip supports 2.5/3.3 v lvttl/lvcmos level signal input power-on strapping pins are input when reset is as serted. they are output during normal operation. external pull-up to vddio_reg for rgmii signal, and to 2.5 v (vddh_reg) for led are recommended. reset and mdio can be pulled up to 2.5 v (vddh_reg) or 3.3 v. sd is typically connected to optical transceiver. sinc e AR8031 integrates the signal detection function in serdes, the pin can be left floating. when the pin is pu lled high, the signal is valid; when pulled low, the signal is lost. input mdc input, internal weak pu input, 2.5 v (3.3 v tolerant) i/o mdio input, internal weak pu i/o, 2.5 v (3.3 v tolerant) input rstn input, no weak pu input, 2.5 v (3.3 v tolerant) output int wol_int output, kept driving low output, based on external pu volatage level i/o clk_25m output, output clock out put, 2.5 v (vddh_reg), can be configured as 1588 reference clock input output pps output, kept driving high 2. 5 v (vddh_reg), internal rtc clock output input sd input, weak pd input, v ih min = 0.7 v, v il max = 0.4 v. input must be lower than 1.4 v. table 3-18. digital pin designs pin type pin description reset asserted re set de-asserted (normal working level)
46 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 46 ? august 2011 company confidential
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 47 ? company confidential august 2011 ? 47 4. register descriptions table 4-1 shows the reset types used in this document. 4.1 register summary three types of registers are present on AR8031: n ieee defined 32 mii registers, referred to as ?registers? in this document ? mii registers are accessed directly through the management frame. n atheros defined debug registers, referred to as ?debug registers? in this document ? write debug offset address to 0x1d ? read/write the data from/to 0x1e n ieee defined mdio manageable device (mmd) register, referred to as ?mmd registers? in this document ? mmd register access: refer to ?mdio interface register? . example: writing 0x8000 to register 0 of mmd3. 1. write 0x3 to register 0xd: 0xd = 0x0003; (function = address; set the device address) 2. write 0x0 to register 0xe: 0xe = 0x0; (set the register offset address) 3. write 0x4003 to register 0xd:0xd=0x4003; (function = data; keep the device address) 4. read register 0xe:0xe == (data from register 0x0 of mmd3) 5. write 0x8000 to register 0xe: 0xe = 0x8000 (write 0x8000 to register 0x0 of mmd3) note: read operation follows the process 1 to 4. 4.2 mii registers table 4-1. reset types type description lh register field with la tching high function. if status is high, then the register is set to one and remains set until a read operation is performed through the management interface or a reset occurs. ll register field with latching low function. if status is low, then the register is cleared to a zero and remains cleared until a read operation is performed through the management interface or a reset occurs. retain value written to a register field takes effect without a software reset. sc self-clear. writing a one to this register causes the desired function to execute immediately, and the register field clears to zero when the function is complete. update the value written to the register field does not take effect until a software reset is executed. the value can still be read after it is written.
48 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 48 ? august 2011 company confidential table 4-2 summarizes the mii registers for the AR8031. table 4-2. register summary offset (hex) register 0x00 ?control register ? copper page? on page 49 ?control ? fiber page? on page 50 0x01 ?status register ? copper page? on page 51 ?status register ? fiber page? on page 53 0x02 ?phy identifier? on page 54 0x03 ?phy identifier2? on page 55 0x04 ?auto-negotiation advertisement register ? copper page? on page 55 ?auto-negotiation advertisement register ? fiber page? on page 57 0x05 ?link partner ability register ? copper page? on page 58 ?link partner ability register ? fiber page? on page 59 0x06 ?auto-negotiation expansion register ? copper page? on page 60 ?auto-negotiation expansion register ? fiber page? on page 61 0x07 ?next page transmit register ? copper page? on page 62 ?next page transmit register ? fiber page for 1000 base-x, sgmii? on page 62 0x08 ?link partner next page register ? copper page? on page 63 ?link partner next page register ? fiber page for 1000 base-x, sgmii? on page 64 0x09 ?1000 base-t control register? on page 64 0x0a ?1000 base-t status register? on page 66 0x0b reserved 0x0c reserved 0x0d ?mmd access control register? on page 67 0x0e ?mmd access address data register? on page 67 0x0f ?extended status register? on page 68 0x10 ?function control register? on page 68 0x11 ?phy-specific status re gister ? copper page? on page 69 ?phy-specific status register ? fiber page? on page 71 0x12 ?interrupt enable register? on page 72 0x13 ?interrupt status register? on page 73 0x14 ?smart speed register? on page 75 0x15 reserved 0x16 ?cable diagnostic tester (cdt) control register? on page 76 0x17 reserved 0x18 ?led control? on page 76 0x19 ?manual led override register? on page 77 0x1a reserved 0x1b ?copper/fiber status register? on page 78 0x1c ?cable diagnostic test er status register? on page 79 0x1d ?debug port (address offset set)? on page 80
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 49 ? company confidential august 2011 ? 49 4.2.1 control register ? copper page offset: 0x00 ? mode: read/write ? 0x1e ?debug port2 (r/w port)? on page 80 0x1f ?chip configure register? on page 80 table 4-2. register summary (continued) offset (hex) register bit name type description 15 reset mode r/w phy software reset. wr iting a "1" to this bit causes the phy the reset operation is done, this bit is cleared to "0" automatically. the rese t occurs immediately. 1 = phy reset 0 = normal operation hw rst. 0 sw rst. sc 14 loopback mode r/w when lo opback is activated, the transmitter data presented on txd is looped back to rxd internally. 1 = enable loopback 0 = disable loopback hw rst. 0 sw rst. 0 13 speed selection (lsb) mode r/w force_speed = {r egister0.6, this bit} 00 = 10mbps 01 = 100mbps 10 = 1000mbps 11 = reserved. hw rst. 1 sw rst. retain 12 auto_ negotiation mode r/w 1 = enable auto-negotiation process 0 = disable auto-negotiation process hw rst. 1 sw rst. retain 11 power_down mode r/w when the port is switched from power down to normal operation, software reset and restart auto-negotiation are performed even when bits reset (0.15) and restart auto- negotiation (0.9) are not set by the user. 1 = power down 0 = normal operation hw rst. 0 sw rst. 0 10 isolate mode r/w the rgmii output pins ar e tristated when this bit is set to 1. the rgmii inputs are ignored. 1 = isolate 0 = normal operation hw rst. 0 sw rst. 0 9restart_auto_ negotiation mode r/w, sc auto-negotiation automatically restarts after hardware or software reset regardless of whether or not the restart bit (0.9) is set. 1 = restart auto-negotiation process 0 = normal operation hw rst. 0 sw rst. 0
50 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 50 ? august 2011 company confidential 4.2.2 control ? fiber page offset: 0x00, or 0d00 ? mode: read/write ? 8 duplex mode mode r/w, sc 1 = full duplex 0 = half duplex hw rst. 1 sw rst. retain 7 collision test mode r/w setting this bit to 1 will ca use the col pin to assert whenever the tx_en pin is asserted. 1 = enable col signal test 0 = disable col signal test hw rst 0 sw rst 0 6 speed selection (msb) mode r/w see bit 0.13. hw rst 0 sw rst 0 5:0 res mode r/o will always be 00000. hw rst 00000 sw rst 00000 bit name type description bit name type description 15 reset mode r/w phy software reset. writing a "1" to this bit causes the phy the reset operation is done, this bit is cleared to "0" automatically. the rese t occurs immediately. 1= phy reset 0 =normal operation hw rst. 0 sw rst. sc 14 loopback mode r/w 100 base-fx, 1000base-x, sgmii loopback.when loopback is activated, 10bit tx d to serdes is looped back to 10bit rxd; 1 = enable loopback 0 = disable loopback hw rst. 0 sw rst. 0 13 speed selection (lsb) mode r/w only for sgmii force speed {bit 0.6, this bit} equals: 00 means 10mbps; 01-means 100mbps, 10-means1000mbps 11-means reserved; these force speed is only valid when 0.12 is 0. hw rst. 0 sw rst. retain 12 auto-negotiation mode r/w for 1000base-x, sgmii: 1 = enable auto-negotiation process 0 = disable auto-negotiation process no auto-negotiation in 100base-fx. hw rst. 1 sw rst. 1
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 51 ? company confidential august 2011 ? 51 4.2.3 status register ? copper page offset: 0x01, or 0d01 ? mode: read/write ? ? 11 power down mode r/w for 1000base-fx, 1000base-x, sgmii mode; when the port is switched from power down to normal operation, software reset and restart auto-negotiation are performed even when bits reset (0.15) and restart auto- negotiation (0.9) are not set by the user. 1 = power down, shut off serdes 0 = normal operation hw rst. 0 sw rst. retain 10 isolate mode r/w not implement. hw rst. 0 sw rst. 0 9 restart auto- negotiation mode r/w, sc for 1000base-x, sgmii. auto-negotiation automatically restarts after hardware or software reset regardless of whether or not the restart bit (0.9) is set. 1 = restart auto-negotiation process 0 = normal operation hw rst. 0 sw rst. sc 8 duplex mode mode r/w, take effect in 1000base-x auto-negotiation disable (this register bit12 is 0) mode, or 100base-fx mode, 1 = full duplex 0 = half duplex hw rst. 1 sw rst. retain 7 collision test mode r/w n/a hw rst. 0 sw rst. 0 6 speed selection (msb) mode r/w see bit 0.13. hw rst. 1 sw rst. retain 5:0 reserved mode r/w will always be 00000. hw rst. 0 sw rst. 0 bit name type description bit name type description 15 100base-t4 mode ro 100base-t4. this protocol is not available. 0 = phy not able to perform 100base-t4 hw rst. always 0 sw rst. always 0 14 100base-x full-duplex mode ro capable of 100 base-tx full duplex operation hw rst. always 1 sw rst. always 1
52 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 52 ? august 2011 company confidential 13 100base-x half-duplex mode ro capable of 100 base-tx half duplex operation hw rst. always 1 sw rst. always 1 12 10 mbps full- duplex mode ro capable of 10 base-t full duplex operation hw rst. always 1 sw rst. always 1 11 10 mbs half-duplex mode ro capable of 10 base-t half duplex operation hw rst. always 1 sw rst. always 1 10 100base-t2 full-duplex mode ro not able to perform 100base-t2 hw rst. always 0 sw rst. always 0 9 100base-t2 half-duplex mode ro not able to perform 100base-t2 hw rst. always 0 sw rst. always 0 8 extended status mode ro extended status information in register15 hw rst. always 1 sw rst. always 1 7 reserved mode ro always be 0. hw rst. always 0 sw rst. always 0 6mf preamble suppression mode ro phy accepts management frames with preamble suppressed hw rst. always 1 sw rst. always 1 5 auto-negotiation complete mode ro 1: auto negotiation process complete 0:auto negotiation process not complete hw rst. 0 sw rst. 0 4 remote fault mode ro, lh 1: remote fault condition detected 0:remote fault condition not detected hw rst. 0 sw rst. 0 3 auto-negotiation ability mode ro 1 = phy able to perform auto negotiation hw rst. 1 sw rst. 1 2 link status mode ro, ll this register bit indicates whether the link was lost since the last read. for the current link status, read register bit 17.10 link real time. 1 = link is up 0 = link is down hw rst. 0 sw rst. 0 bit name type description
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 53 ? company confidential august 2011 ? 53 4.2.4 status register ? fiber page offset: 0x01, or 0d01 ? mode: read/write ? ? 1 jabber detect mode ro, lh 1: jabber condition detected 0: jabber condition not detected hw rst. 0 sw rst. 0 0 extended capability mode ro 1: ex tended register capabilities hw rst. always 1 sw rst. always 1 bit name type description bit name type description 15 100base-t4 mode ro 100 base-t4. this protocol is not available. 0 = phy not able to perform 100base-t4 hw rst. always 0 sw rst. always 0 14 100base-x full-duplex mode ro capable of 100 base-fx full duplex operation hw rst. always 1 sw rst. always 1 13 100base-x half-duplex mode ro capable of 100 base-fx half duplex operation hw rst. always 1 sw rst. always 1 12 10 mbps full- duplex mode ro capable of 10 base-x full duplex operation hw rst. always 0 sw rst. always 0 11 10 mbs half-duplex mode ro capable of 10 base-x half duplex operation hw rst. always 0 sw rst. always 0 10 100base-t2 full-duplex mode ro not able to perform 100base-t2 hw rst. always 0 sw rst. always 0 9 100base-t2 half-duplex mode ro not able to perform 100base-t2 hw rst. always 0 sw rst. always 0 8 extended status mode ro extended st atus information in register15 hw rst. always 1 sw rst. always 1
54 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 54 ? august 2011 company confidential 4.2.5 phy identifier offset: 0x02, or 0d02 ? mode: read/write ? ? 7 reserved mode ro always be 0. hw rst. always 0 sw rst. always 0 6mf preamble suppression mode ro phy accepts management frames with preamble suppressed hw rst. always 1 sw rst. always 1 5 auto-negotiation complete mode ro 1: auto negotiation process complete 0:auto negotiation process not complete hw rst. 0 sw rst. 0 4 remote fault mode ro, lh 1 = remote fault condition detected 0 = remote fault condition not detected hw rst. 0 sw rst. 0 3 auto-negotiation ability mode ro 1 = phy able to perform auto negotiation hw rst. always 1 sw rst. always 1 2 link status mode ro, ll this register bit indicates whether the link was lost since the last read. for the current link status, read register bit 17.10 link real time. 1 = link is up 0 = link is down hw rst. 0 sw rst. 0 1 jabber detect mode ro, lh 1 = jabber condition detected 0 = jabber condition not detected hw rst. 0 sw rst. 0 0 extended capability mode ro 1 = ex tended register capabilities hw rst. always 1 sw rst. always 1 bit name type description bit name type description 15:0 organizationally unique identifier bit 3:18 mode ro organizationally uniq ue identifier bits 3:18 hw rst. always 004d sw rst. always 004d
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 55 ? company confidential august 2011 ? 55 4.2.6 phy identifier2 offset: 0x03, or 0d03 ? mode: read/write 4.2.7 auto-negotiation advertisement register ? copper page offset: 0x04, or 0d04 ? mode: read/write ? bit name type description 15:0 organizationally unique identifier lsb. model number revision number mode ro organizationally uniq ue identifier bits 19:24 hw rst. always 0xd074 sw rst. always 0xd074 bit name type description 15 next page mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down if 1000base-t is advertised th en the required next pages are automatically transmitted. register 4.15 should be set to 0 if no additional next pages are needed. 1 = advertise 0 = not advertised hw rst. 0 sw rst. update 14 ack mode ro must be 0 hw rst. always 0 sw rst. always 0 13 remote fault mode r/w 1 = set remote fault bit 0 = do not set remote fault bit hw rst. 0 sw rst. update 12 xnp_able mode r/w extended next page enable control bit: 1 = local device supports transmission of extended next pages; 0 = local device does not support transmission of extended next pages. hw rst. always 1 sw rst. retain
56 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 56 ? august 2011 company confidential 11 asymmetric pause mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down 1 = asymmetric pause 0 = no asymmetric pause hw rst. 1 sw rst. update 10 pause mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down 1 = mac pause implemented 0 = mac pause not implemented hw rst. 1 sw rst. update 9 100base-t4 mode ro not able to perform 100base-t4 hw rst. always 0 sw rst. always 0 8 100base-tx full duplex mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down 1 = advertise 0 = not advertised hw rst. 1 sw rst. update 7 100base-tx half duplex mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down 1 = advertise 0 = not advertised hw rst. 1 sw rst. update bit name type description
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 57 ? company confidential august 2011 ? 57 4.2.8 auto-negotiation advertisement register ? fiber page offset: 0x04, or 0d04 ? mode: read/write ? ? 6 10base-tx full duplex mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down 1 = advertise 0 = not advertised hw rst. 1 sw rst. update 5 10base-tx half duplex mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down 1 = advertise 0 = not advertised hw rst. 1 sw rst. update 4:0 selector field mode ro selector field mode 00001 = 802.3 hw rst. always 00001 sw rst. always 00001 bit name type description bit name type description 15 next page mode r/w this bit index if additional next pages are needed. 1 = advertise 0 = not advertised hw rst. 0 sw rst. update 14 ack mode ro must be 0 hw rst. always 0 sw rst. always 0 13:12 remote fault mode r/w 00 = link_ok 01=offline 10=link_failure 11=auto_error hw rst. 00 sw rst. update
58 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 58 ? august 2011 company confidential 4.2.9 link partner ability register ? copper page offset: 0x05, or 0d05 ? mode: read/write 11:9 reserved mode r/w hw rst. 0 sw rst. 0 8 asymmetric pause mode r/w 1 = asymmetric pause 0 = no asymmetric pause hw rst. 1 sw rst. update 7 pause mode r/w 1 = mac pause implemented 0 = mac pause not implemented hw rst. 1 sw rst. update 6 1000base-x half duplex mode r/w 1000base-t half duplex ability. hw rst. 0 sw rst. retain 5 1000base-x full duplex mode r/w 1000base-t full duplex ability. hw rst. 1 sw rst. retain 4:0 reserved mode ro hw rst. always 00000 sw rst. always 00000 bit name type description bit name type description 15 next page mode ro received code word bit 15 1 = link partner capable of next page 0 = link partner not capable of next page hw rst. 0 sw rst. 0 14 ack mode ro acknowledge received code word bit 14 1 = link partner received link code word 0 = link partner does not have next page ability hw rst. 0 sw rst. 0 13 remote fault mode ro remote fault received code word bit 13 1 = link partner detected remote fault 0 = link partner has not detected remote fault hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 59 ? company confidential august 2011 ? 59 4.2.10 link partner ability register ? fiber page offset: 0x05, or 0d05 ? mode: read/write 12 reserved mode ro technology ability field received code word bit 12 hw rst. 0 sw rst. 0 11 asymmetric pause mode ro technology ability field received code word bit 11 1 = link partner requests asymmetric pause 0 = link partner does not request asymmetric pause hw rst. 0 sw rst. 0 10 pause mode ro technology ability field received code word bit 10 1 = link partner is capable of pause operation 0 = link partner is not ca pable of pause operation hw rst. 0 sw rst. 0 9 100base-t4 mode ro technology ability field received code word bit 9 1 = link partner is 100base-t4 capable 0 = link partner is not 100base-t4 capable hw rst. 0 sw rst. 0 8 100base-tx full duplex mode ro technology ability field received code word bit 8 1 = link partner is 100bas e-tx full-duplex capable 0 = link partner is not 100base-tx full-duplex capable hw rst. 0 sw rst. 0 7 100base-tx half duplex mode ro technology ability field received code word bit 7 1 = link partner is 100base-tx half-duplex capable 0 = link partner is not 100base-tx half-duplex capable hw rst. 0 sw rst. 0 6 10base-t full duplex mode ro technology ability field received code word bit 6 1 = link partner is 10base-t full-duplex capable 0 = link partner is not 10base-t full-duplex capable hw rst. 0 sw rst. 0 5 10base-t half duplex mode ro technology ability field received code word bit 5 1 = link partner is 10base-t half-duplex capable 0 = link partner is not 10base-t half-duplex capable hw rst. 0 sw rst. 0 4:0 selector field mode ro selector field received code word bit 4:0 hw rst. 00000 sw rst. 00000 bit name type description
60 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 60 ? august 2011 company confidential 4.2.11 auto-negotiation expansion register ? copper page offset: 0x06, or 0d06 ? mode: read/write ? bit name type description 15 next page mode ro received code word bit 15 1 = link partner capable of next page 0 = link partner not capable of next page hw rst. 0 sw rst. 0 14 ack mode ro acknowledge received code word bit 14 1 = link partner received link code word 0 = link partner does not have next page ability hw rst. 0 sw rst. 0 13:12 remote fault mode ro remote fault received code word bit 13,12 hw rst. 0 sw rst. 0 11:9 reserved mode ro hw rst. 0 sw rst. 0 8 asymmetric pause mode ro technology ability field received code word bit 8 1 = link partner requests asymmetric pause 0 = link partner does not request asymmetric pause hw rst. 0 sw rst. 0 7 pause mode ro technology ability field received code word bit 7 1 = link partner is capable of pause operation 0 = link partner is not capable of pause operation hw rst. 0 sw rst. 0 6 1000 base-x half duplex mode ro technology ability field received code word bit 6 1 = link partner is 1000basex half duplex capable 0 = link partner is not 1000basex half duplex capable hw rst. 0 sw rst. 5 1000 base-x full duplex mode ro technology ability field received code word bit 6 1 = link partner is 1000basex full duplex capable 0 = link partner is not 1000b asex full duplex capable hw rst. 0 sw rst. 0 4:0 reserved mode ro hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 61 ? company confidential august 2011 ? 61 4.2.12 auto-negotiation expansion register ? fiber page offset: 0x06, or 0d06 ? mode: read/write ? ? bit name type description 15:5 reserved mode ro res erved. must be 0. hw rst. 0x000 sw rst. 0x000 4 parallel detection fault mode ro 1: a fault has been detect 0: no fault has been detected hw rst. 0 sw rst. 0 3 link partner next page able mode ro 1: link partner is next page able 0: link partner is not next page able hw rst. 0 sw rst. 0 2 local next page able mode ro 1 = local device is next page able hw rst. 1 sw rst. 1 1 page received mode ro, lh 1: a new page has been received 0: no new page has been received hw rst. 0 sw rst. 0 0 link partner auto - negotiation able mode ro 1: link partner is auto negotiation able 0: link partner is no t auto negotiation able hw rst. 0 sw rst. 0 bit name type description 15:4 reserved mode ro res erved. must be 0. hw rst. 0x000 sw rst. 0x000 3 link partner next page able mode ro for 1000bx, sgmii; 1 = link partner is next page able 0 = link partner is not next page able hw rst. 0 sw rst. 0
62 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 62 ? august 2011 company confidential 4.2.13 next page transmit register ? copper page offset: 0x07, or 0d07 4.2.14 next page transmit register ? fiber page for 1000 base-x, sgmii 2 local next page able mode ro for 1000bx, sgmii; 1 = local device is next page able hw rst. 1 sw rst. 1 1 page received mode ro for 1000bx, sgmii; 1 = a new page has been received 0 = no new page has been received hw rst. 0 sw rst. 0 0 link partner auto negotiation able mode ro, lh for 1000bx, sgmii; 1 = link partner is auto negotiation able 0 = link partner is not auto negotiation able hw rst. 0 sw rst. 0 bit name type description bit name type description 15 next page mode r/w transmit code word bit 15 hw rst. 0 sw rst. 0 14 reserved mode r/w transmit code word bit 14 hw rst. 0 sw rst. 0 13 message page mode mode r/w transmit code word bit 13 hw rst. 1 sw rst. 1 12 ack2 mode r/w transmit code word bit 12 hw rst. 1 sw rst. 1 11 toggle mode ro transmit code word bit 11 hw rst. 0 sw rst. 0 10:0 message/ unformatted field mode r/w transmit code word bit 10:0 hw rst. 0x001 sw rst. 0x001
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 63 ? company confidential august 2011 ? 63 offset: 0x07, or 0d07 4.2.15 link partner next page register ? copper page offset: 0x08, or 0d08 bit name type description 15 next page mode r/w transmit code word bit 15 hw rst. 0 sw rst. 0 14 reserved mode r/w transmit code word bit 14 hw rst. 0 sw rst. 0 13 message page mode mode r/w transmit code word bit 13 hw rst. 1 sw rst. 1 12 ack2 mode r/w transmit code word bit 12 hw rst. 0 sw rst. 0 11 toggle mode ro transmit code word bit 11 hw rst. 0 sw rst. 0 10:0 message/ unformatted field mode r/w transmit code word bit 10:0 hw rst. 0x001 sw rst. 0x001 bit name type description 15 next page mode ro received code word bit 15 hw rst. 0 sw rst. 0 14 reserved mode ro received code word bit 14 hw rst. 0 sw rst. 0 13 message page mode mode ro received code word bit 13 hw rst. 0 sw rst. 0 12 ack2 mode ro received code word bit 12 hw rst. 1 sw rst. 1
64 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 64 ? august 2011 company confidential 4.2.16 link partner next page register ? fiber page for 1000 base-x, sgmii offset: 0x08, or 0d08 4.2.17 1000 base-t control register 11 toggle mode ro received code word bit 11 hw rst. 1 sw rst. 1 10:0 message/ unformatted field mode ro received code word bit 10:0 hw rst. 0 sw rst. 0 bit name type description bit name type description 15 next page mode ro received code word bit 15 hw rst. 0 sw rst. 0 14 reserved mode ro received code word bit 14 hw rst. 0 sw rst. 0 13 message page mode mode ro received code word bit 13 hw rst. 0 sw rst. 0 12 ack2 mode ro received code word bit 12 hw rst. 0 sw rst. 0 11 toggle mode ro received code word bit 11 hw rst. 0 sw rst. 0 10:0 message/ unformatted field mode ro received code word bit 10:0 hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 65 ? company confidential august 2011 ? 65 offset: 0x09, or 0d09 bit name type description 15:13 test mode mode r/w after exiting the test mode, hardware reset or software reset (register 0.15) should be issued to ensure normal operation. 000 = normal mode 001 = test mode 1 - transmit waveform test 010 = test mode 2 - transmit jitter test (master mode) 011 = test mode 3 - transmit jitter test (slave mode) 100 = test mode 4 - tr ansmit distortion test 101, 110, 111 = reserved hw rst. 000 sw rst. retain 12 master/slave manual configuration enable mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down 1 = manual master/slave configuration 0 = automatic master/slave configuration hw rst. 0 sw rst. update 11 master/slave configuration mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down register 9.11 is ignored if register 9.12 is equal to 0. 1 = manual configure as master 0 = manual configure as slave hw rst. 0 sw rst. update 10 port type mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down register 9.10 is ignored if register 9.12 is equal to 1. 1 = prefer multi-port device (master) 0 = prefer single port device (slave) hw rst. 0 sw rst. update
66 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 66 ? august 2011 company confidential 4.2.18 1000 base-t status register offset: 0x0a, or 0d10 9 1000base-t full duplex mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down 1 = advertise 0 = not advertised hw rst. 1 sw rst. update 8 1000base-t half-duplex mode r/w the value of this bit will be updated immediately after writing this register. but the value written to this bit does not takes effect until any one of the following occurs: n software reset is asserted (register 0.15) n restart auto-negotiation is asserted (register 0.9) n power down (register 0.11) transitions from power down to normal operation n link goes down 1 = advertise 0 = not advertised note: the default setting is no 1000base-t/half duplex advertised. hw rst. 0 sw rst. update 7:0 reserved mode r/w hw rst. 0 sw rst. 0 bit name type description bit name type description 15 master/slave configuration fault mode ro, lh this register bit will clear on read 1 = master/slave configuration fault detected 0 = no fault detected hw rst. 0 sw rst. 0 14 master/slave configuration resolution mode ro this register bit is not valid until register 6.1 is 1. 1 = local phy configuration resolved to master 0 = local phy configuration resolved to slave hw rst. 0 sw rst. 0 13 local receiver status mode ro 1 = local receiver ok 0 = local receiver not ok hw rst. 0 sw rst. 0 12 remote receiver status mode ro 1 = remote receiver ok 0 = remote receiver not ok hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 67 ? company confidential august 2011 ? 67 4.2.19 mmd access control register offset: 0x0d, or 0d13 4.2.20 mmd access address data register offset: 0x0e, or 0d14 11 link partner 1000 base-t full duplex capability mode ro this register bit is not valid until register 6.1 is 1. 1 = link partner is capable of 1000 base-t half duplex 0 = link partner is not capable of 1000 base-t half duplex hw rst. 0 sw rst. 0 10 link partner 1000 base-t half duplex capability mode r/w this register bit is not valid until register 6.1 is 1. 1 = link partner is capable of 1000 base-t full duplex 0 = link partner is not capa ble of 1000 base-t full duplex hw rst. 0 sw rst. 0 9:8 reserved mode ro reserved. hw rst. always 0 sw rst. always 0 7:0 idle error count mode ro, sc msb of idle error counter these register bits report the idle error count since the last time this register was read. the counter pegs at 11111111 and will not roll over. hw rst. 0 sw rst. 0 bit name type description bit name type description 15:14 function mode r/w 00 = address 01 = data, no post increment 10 = data, post increment on reads and writes 11 = data, post increment on writes only; hw rst. 0 sw rst. 0 13:5 reserved mode ro hw rst. 0 sw rst. 0 4:0 devad mode r/w device address hw rst. 0 sw rst. update
68 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 68 ? august 2011 company confidential 4.2.21 extended status register offset: 0x0f, or 0d15 4.2.22 function control register offset: 0x10, or 0d16 bit name type description 15:14 address data mode r/w if register13.15: 14=00, mmd devad's address register. otherwise, mmd devad's data register as indicated by the contents of its address register hw rst. 00 sw rst. retain bit name type description 15 1000base-x full duplex mode ro phy not able to perform 1000base-x full duplex hw rst. always 1 sw rst. always1 14 1000base-x half duplex mode ro phy not able to perform 1000base-x half duplex hw rst. always0 sw rst. always0 13 1000base-t full-duplex mode ro phy able to perform 1000base-t full duplex hw rst. always 1 sw rst. always 1 12 1000base-t half-duplex mode r/w phy not able to perform 1000base-t half duplex hw rst. always0 sw rst. always0 11:0 reserved mode ro reserved. hw rst. always0 sw rst. always0 bit name type description 15:12 reserved mode r/w hw rst. 0 sw rst. retain 11 assert crs on transmit mode r/w this bit has effect on ly in 10bt half-duplex mode: 1 = assert on transmitting or receiving; 0 = never assert on transmitting, only assert on receiving. hw rst. 1 sw rst. retain
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 69 ? company confidential august 2011 ? 69 4.2.23 phy-specific status register ? copper page offset: 0x11, or 0d17 10 force_link mode r/w 1 = when an_en bit (0.12) is 1, force 10bt link up; 0 = normal mode; hw rst. 0 sw rst. retain 9:7 reserved mode r/w hw rst. 0 sw rst. retain 6:5 mdi crossover mode mode r/w changes to these bits ar e disruptive to the normal operation; therefore any changes to these registers must be followed by a software reset to take effect. 00 = manual mdi configuration 01 = manual mdix configuration 10 = reserved 11 = enable automatic crossover for all modes hw rst. 11 sw rst. update 4:3 reserved mode ro hw rst. 0 sw rst. 0 2 sqe test mode r/w sqe test is automatically disabled in full-duplex mode regardless of the state of register 16.2 1 = sqe test enabled 0 = sqe test disabled hw rst. 0 sw rst. retain 1 polarity reversal mode r/w if polarity is disa bled, then the polarity is forced to be normal in 10base-t. 1 = polarity reversal disabled 0 = polarity reversal enabled hw rst. 1 sw rst. retain 0 disable jabber mode ro jabber has effect only in 10base-t half-duplex mode. 1 = disable jabber function 0 = enable jabber function hw rst. 0 sw rst. retain bit name type description bit name type description 15:14 speed mode r/w these status bits are vali d only after resolved bit 17.11 = 1. the resolved bit is set when auto-negotiation is completed or auto-negotiation is disabled. 11 = reserved 10 = 1000 mbps 01 = 100 mbps 00 = 10 mbps hw rst. 0 sw rst. retain
70 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 70 ? august 2011 company confidential 13 duplex mode ro this status bit is valid on ly after resolved bit 17.11 = 1. the resolved bit is set when auto-negotiation is completed or auto-negotiation is disabled. 1 = full-duplex 0 = half-duplex hw rst. 0 sw rst. retain 12 page received (real-time) mode ro 1 = page received 0 = page not received hw rst. 0 sw rst. retain 11 speed and duplex resolved mode ro when auto-negotiat ion is not enabled, 17.11 = 1 for force speed mode. 1 = resolved 0 = not resolved hw rst. 0 sw rst. 0 10 link (real-time) mode ro 1 = link up 0 = link down hw rst. 0 sw rst. 0 9:7 reserved mode ro always 0 hw rst. 0 sw rst. 0 6mdi crossover status mode ro this status bit is valid only after resolved bit 17.11 = 1. the resolved bit is set when auto-negotiation is completed or auto-negotiation is disabled. this bit is 0 or 1 depending on what is written to 16.6:5 in manual configuration mode. register 16.6:5 are updated with software reset. 1 = mdix 0 = mdi hw rst. 0 sw rst. retain 5 wirespeed downgrade mode r/w 1 = downgrade 0 = no downgrade hw rst. 0 sw rst. retain 4 reserved mode ro hw rst. 1 sw rst. retain 3transmit pause enabled mode ro this is a reflection of the mac pause resolution. this bit is for information purposes and is not used by the device. this status bit is valid only after resolved bit 17.11 = 1. the resolved bit is set when auto-negotiation is completed; while in force mode, this bit is set to be 0. 1 = transmit pause enabled 0 = transmit pause disabled hw rst. 0 sw rst. retain 2 receive pause enabled mode ro this is a reflection of the mac pause resolution. this bit is for information purposes and is not used by the device. this status bit is valid only after resolved bit 17.11 = 1. the resolved bit is set when auto-negotiation is completed; while in force mode, this bit is set to be 0. 1 = receive pause enabled 0 = receive pause disabled hw rst. 0 sw rst. retain bit name type description
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 71 ? company confidential august 2011 ? 71 4.2.24 phy-specific status register ? fiber page offset: 0x11, or 0d17 1 polarity (real time) mode ro 1 = reverted. 0 = normal hw rst. 0 sw rst. retain 0 jabber (real time) mode ro 1 = jabber 0 = no jabber hw rst. 0 sw rst. retain bit name type description bit name type description 15:14 speed mode ro 11 = reserved 10 = 1000 mbps 01 = 100 mbps 00 = 10 mbps hw rst. 10 sw rst. retain 13 duplex mode ro 1 = full-duplex 0 = half-duplex hw rst. 1 sw rst. retain 12 page received (real-time) mode ro 1 = page received 0 = page not received hw rst. 0 sw rst. retain 11 speed and duplex resolved mode ro when auto-negotiat ion is not enabled, 17.11 = 1 for force speed mode. 1 = resolved 0 = not resolved hw rst. 0 sw rst. 0 10 link (real-time) mode ro for 1000base-x, 100base-fx: 1 = link up 0 = link down hw rst. 0 sw rst. 0 9 mr_an_complete mode ro for 1000base-x, sgmii: 1 = auto-negotiation complete 0 = auto-negotiation not complete hw rst. 0 sw rst. 0 8 sync_status mode ro for 1000base-x, sgmii 1 = sgmii_basex is sync 0 = sgmii_basex is not sync hw rst. 0 sw rst. 0 7:4 reserved mode ro hw rst. 0 sw rst. 0
72 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 72 ? august 2011 company confidential 4.2.25 interrupt enable register offset: 0x12, or 0d18 3transmit pause enabled mode ro this is a reflection of the mac pause resolution. this bit is for information purposes and is not used by the device. this status bit is valid only after resolved bit 17.11 = 1. the resolved bit is set when auto-negotiation is completed; while in force mode, this bit is set to be 0. 1 = transmit pause enabled 0 = transmit pause disabled hw rst. 0 sw rst. retain 2 receive pause enabled mode ro this is a reflection of the mac pause resolution. this bit is for information purposes and is not used by the device. this status bit is valid only after resolved bit 17.11 = 1. the resolved bit is set when auto-negotiation is completed; while in force mode, this bit is set to be 0. 1 = receive pause enabled 0 = receive pause disabled hw rst. 0 sw rst. retain 1:0 reserved mode ro hw rst. 0 sw rst. 0 bit name type description bit name type description 15 auto-negotiation error mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 14 speed changed mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 13 reserved mode r/w hw rst. 0 sw rst. retain 12 page received mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 11 link fail interrupt mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 10 link success interrupt mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 73 ? company confidential august 2011 ? 73 4.2.26 interrupt status register offset: 0x13, or 0d19 9 fast link down[1] mode r/w 1 = interrupt eanble, must be enabled with bit[6], fast link down[0]together 0 = interrupt disable hw rst. 0 sw rst. retain 8 link_fail_bx mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 7 link_success_bx mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 6 fast link down[0] mode r/w must be enabled to gether with bit[9] fast link down[1] 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 5 wirespeed- downgrade interrupt mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 4 int_10ms_ptp mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 3 int_10rx_ptp mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 2 int_tx_ptp mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 1 polarity changed mode r/w 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain 0 int_wol_ptp mode r/w wake-on-lan interrupt 1 = interrupt enable 0 = interrupt disable hw rst. 0 sw rst. retain bit name type description
74 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 74 ? august 2011 company confidential bit name type description 15 auto-negotiation error mode ro, lh error may occur if ei ther master/slave does not resolve, or no common hcd, or link does not come up after negotiation is complete. 1 = auto-negotiation error 0 = no auto-negotiation error hw rst. 0 sw rst. retain 14 speed changed mode ro, lh 1 = speed changed 0 = speed unchanged hw rst. 0 sw rst. retain 13 reserved mode ro, lh hw rst. 0 sw rst. retain 12 page received mode ro, lh 1 = page received 0 = page not received hw rst. 0 sw rst. retain 11 link fail interrupt mode ro, lh 1 = base-t link down takes place. 0 = no link is down. hw rst. 0 sw rst. retain 10 link success interrupt mode ro, lh 1 = base-t link up takes place. 0 = no link is up. hw rst. 0 sw rst. retain 9 fast link down[1] mode ro, lh cooperate with bit[6] to show different speed interrupt hw rst. 0 sw rst. retain 8 link_fail_bx mode ro, lh 1 = 1000 base-x / 100 base-fx link down takes place. 0 = no 1000 base-x / 100 base-fx link is down. hw rst. 0 sw rst. retain 7 link_success_bx mode ro, lh 1 = 1000 base-x / 100 base-f x link up takes place. 0 = no 1000 base-x / 100 base-fx link is up. hw rst. 0 sw rst. retain 6 fast link down[0] mode ro, lh work with bit[9] to show fast link down interrupt [bit9, bit6] 2?b00 = without fast link down 2?b01 = 10 base-t fast link down happened 2?b01 = 100 base-t fast link down happened 2?b10 = 1000 base-t fast link down happened hw rst. 0 sw rst. retain 5 wirespeed- downgrade interrupt mode ro, lh 1 = wirespeed-downgrade detected 0 = no wirespeed-downgrade detected hw rst. 0 sw rst. retain
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 75 ? company confidential august 2011 ? 75 4.2.27 smart speed register offset: 0x14, or 0d20 4 int_10ms_ptp mode ro, lh 1 = count to 10ms interrupt happened. 0 = interrupt not happened. hw rst. 0 sw rst. retain 3 int_rx_ptp mode ro, lh 1 = recied ptp message interrupt happened. 0 = recieve ptp message interrupt not happened. hw rst. 0 sw rst. retain 2 int_tx_ptp mode ro, lh 1 = transmit ptp message interrupt happened 0 = tranmit ptp message interrupt not happened hw rst. 0 sw rst. retain 1 polarity changed mode ro, lh 1 = polarity changed 0 = polarity not changed hw rst. 0 sw rst. retain 0 int_wol_ptp mode ro, lh 1 = wake-on-lan packet received 0 = no wake-on-lan packet received hw rst. 0 sw rst. retain bit name type description bit name type description 15:6 reserved mode r0 reser ved. must be 00000000. hw rst. 0 sw rst. 0 5 smartspeed_en mode r/w the default value is on e; if this bit is set to one and cable inhibits completion of the training phase, then after a few failed attempts, the attansic card automatically downgrades the highest ability to the next lower speed: from 1000 to 100 to 10. hw rst. 1 sw rst. update 4:2 smartspeed_retry_li mit mode r/w the default value is three; if these bits are set to three, then the attansic card will attempt five times before downgrading; the number of attempts can be changed through setting these bits. hw rst. 011 sw rst. update 1 bypass_smartspeed _timer mode r/w the default value is zero; if this bit is set to one, the smartspeed fsm will bypass the timer used for stability. hw rst. 0 sw rst. update 0 reserved mode ro reserved. must be 0. hw rst. 0 sw rst. 0
76 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 76 ? august 2011 company confidential 4.2.28 cable diagnostic tester (cdt) control register offset: 0x16, or 0d22 4.2.29 led control offset: 0x018, or 0d24 ? bit name type description 15:10 reserved mode r0 reserved. hw rst. always 0 sw rst. always 0 9:8 mdi pair select mode r/w cdt control registers. use the cdt control registers to select which mdi pair is shown in the cdt status register. 00 = mdi[0] pair 01 = mdi[1] pair 10 = mdi[2] pair 11 = mdi[3] pair hw rst. 00 sw rst. retain 7:1 reserved mode r/w always 0 hw rst. 0 sw rst. 0 0 enable test mode r/w when set, hardware automatically disable this bit when cdt is done. 1 = enable cdt test 0 = disable cdt test hw rst. 0 sw rst. retain bit name type description 15 disable led mode r/w contr ol led_link10_100, led_act 0 = enable 1 = disable hw rst. 0 sw rst retain 14:12 led on time mode r/w led_act active duty cycle. 000 = 5 ms 001 = 10 ms 010 = 21 ms 011 = 42 ms 100 = 84 ms 101 = 168 ms 110 to 111 = 42ms hw rst. 011 sw rst retain 11 reserved mode ro reserved hw rst. 0 sw rst 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 77 ? company confidential august 2011 ? 77 4.2.30 manual led override register offset: 0x19, or 0d25 10:8 led off time mode r/w led _act active duty cycle. 000 = 21 ms 001 = 42 ms 010 = 84 ms 011 = 168 ms 100 = 330 ms 101 = 670 ms 110 to 111 = 168ms hw rst. 010 sw rst retain 7:5 reserved mode ro reserved hw rst. 000 sw rst always 0 4:3 led_link control mode r/w 00 = direct led mode (default) 11 = disable led_link10_100 only 01, 10 = reserved hw rst. 00 sw rst retain 2 led_act control mode r/w 0 = normal 1 = led_act blin ks when linked hw rst. 0 sw rst retain 1 reserved mode r/w reserved hw rst. 0 sw rst retain 0 reserved mode r/w reserved hw rst. 0 sw rst retain bit name type description bit name type description 15:13 reserved mode r/w reserved hw rst. 001 sw rst retain 12 led_act control mode r/w 1 = link/active. wh en link is established, led_act is on. when link is active, led_act blinks. 0 = active. when link is established, led_act is off. when link is active, led_act blinks. the blink duty cycle is contro lled by led control register (0x18). hw rst. 1 sw rst retain 11:10 reserved mode r/w reserved hw rst. 00 sw rst retain
78 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 78 ? august 2011 company confidential 4.2.31 copper/fiber status register offset: 0x01b, or 0d27 ? 9:8 reserved mode r/w reserved hw rst. 00 sw rst retain 7:6 led_link10_100 control mode r/w 00 = normal 01 = led_act blinks 10 = led off 11 = led on led_act can be turned off by regster 0x19 bit[3:0] hw rst. 00 sw rst retain 5:4 reserved mode r/w reserved hw rst. 00 sw rst retain 3:2 led_rx mode r/w 00 = normal 01 = blink 10 = led off 11 = led on led_act status = led_tx|led_rx when both led_rx and led_tx are set to 10, led_act is turned off; when either is set to 01, led_act blinks; when either is set to 11, led_act is on. hw rst. 00 sw rst retain 1:0 led_tx mode r/w 00 = normal 01 = blink 10 = led off 11 = led on when both led_rx and led_tx are set to 10, led_act is turned off; when either is set to 01, led_act blinks; when either is set to 11, led_act is on. hw rst. 00 sw rst retain bit name type description bit name type description 15:14 reserved mode r/w hw rst. 0 sw rst 0 13 transmit_pause _en_bx mode r/w hw rst. 0 sw rst 0 12 receive_pause _en_bx mode ro hw rst. 0 sw rst 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 79 ? company confidential august 2011 ? 79 4.2.32 cable diagnostic tester status register offset: 0x1c, or 0d28 ? 11 link_established _bx mode ro link status of fiber hw rst. 0 sw rst 0 10 fd_mode_bx mode ro dupl ex mode of fiber hw rst. 1 sw rst always 1 9:8 speed_mode_bx mode r/w speed_mode of fiber, only 2 cases: 10 = 1000bx 01 = 100fx hw rst. 2?b10 sw rst 2?b10 7:6 reserved mode ro hw rst. 0 sw rst 0 5transmit_pause _en_bt mode ro hw rst. 0 sw rst 0 4receive_pause _en_bt mode ro hw rst. 0 sw rst 0 3 link_established _bt mode ro link status of copper hw rst. 0 sw rst 0 2 fd_mode_bt mode ro duplex mode of copper hw rst. 0 sw rst 0 1:0 speed_mode_bt mode ro speed_mode of copper: 2'b00:10bt, 2'b01:100bt, 2'b10:1000bt, 2'b11:reserved; hw rst. 0 sw rst 0 bit name type description bit name type description 15:10 reserved mode ro reserved. hw rst. always 0 sw rst. always 0
80 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 80 ? august 2011 company confidential 4.2.33 debug port (address offset set) offset: 0x1d, or 0d29 ? 4.2.34 debug port2 (r/w port) offset: 0x1e, or 0d30 ? 4.2.35 chip configure register offset: 0x1f, or 0d31 ? 9:8 status mode ro the content of the cdt status registers applies to the cable pair selected in the cdt control registers. 11 = test fail 00 = valid test, normal cable (no short or open in cable) 10 = valid test, open in cable (impedance > 333 ohms) 01 = valid test, short in cable (impedance < 33 ohms) hw rst. 00 sw rst. 00 7:0 delta_time mode ro delta time to indicate distance. hw rst. 0 sw rst. 0 bit name type description bit name type description 15:6 reserved mode ro the address index of the register will be write or read. hw rst. 0 sw rst. 0 5:0 address offset mode r/w the ad dress index of the register will be write or read. hw rst. 0 sw rst. 0 bit name type description 15:0 debug data port mode r/w the da ta port of debug register. before access this register, must set the address offset first. hw rst. 0 sw rst. 0 bit name type description 15 bt_bx_reg_sel mode r/w pos pin. copper page fiber page select bit: 1 = select copper page registers 0 = select fiber page registers hw rst. sec sw rst. retain
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 81 ? company confidential august 2011 ? 81 14 smii_imp_50_75_aut o mode r/w rx/tx impedance of serdes in auto media select mode. 1 = 75 ? 0 = 50 ? hw rst. 0 sw rst. retain 13 sgmii_rximp_ 50_75 mode r/w pos pin. rx impedance of serdes 1 = 75 ? 0 = 50 ? hw rst. sec. sw rst. retain 12 sgmii_tximp_ 50_75 mode r/w pos pin. tx impedance of serdes 1 = 75 ? 0 = 50 ? hw rst. sec. sw rst. retain 11 reserved mode reserved hw rst. sw rst. 10 priority_sel mode r/w media preferen ce in auto media select mode. 1 = prefer copper 0 = prefer fiber hw rst. 0 sw rst. retain 9 reserved mode reserved hw rst. sw rst. 8 fiber_mode_auto mode r/w fiber mode in auto media select mode. 1 = 1000 base-x fiber 0 = 100 base-fx fiber hw rst. 1 sw rst. retain 7:4 mode_cfg_qual mode ro if mode_cfg is not set to auto media detect mode (rg_auto_mdet), mode_cfg_q ual is equal to mode_cfg. if mode_cfg is set to auto media detect mode: n when auto media select is finished, mode_cfg is set to actual internal mode. if co pper is up, mdoe_cfg_qual is baset_rgmii; if fiber is up, mode_cfg_qual is fx100_rgmii_75/50 or bx1000_rgmii_75/50. n when auto media select is not done, or no copper or copper link is present, mode_cfg_qual is rg_auto_mdet. hw rst. 0 sw rst. 0 bit name type description
82 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 82 ? august 2011 company confidential 3:0 mode_cfg mode r/w pos pin. chip mode configure bits; 0000 = baset_rgmii 0001 = baset_sgmii; 1110 = fx100_rgmii_75; 0110 = fx100_rgmii_50; 1111 = fx100_conv_75; 0111 = fx100_conv_50; 0011 = bx1000_rgmii_75; 0010 = bx1000_rgmii_50; 0101 = bx1000_conv_75; 0100 = bx1000_conv_50; 1011 = rg_auto_mdet; others: reserved. hw rst. see desc. sw rst. retain bit name type description
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 83 ? company confidential august 2011 ? 83 4.3 debug register descriptions table 4-3 summarizes the debug registers for the AR8031. 4.3.1 analog test control offset: 0x00 (hex), or 0 (decimal) ? 4.3.2 serdes test and system mode control offset: 0x05 (hex) or 05 (decimal) ? table 4-3. debug register summary offset register 0x00 ?analog test control? on page 83 0x05 ?serdes test and system mode control? on page 83 0x10 ?100base-tx test mode select? on page 84 0xb ?hib control and auto-negotiation test register? on page 85 0x11 ?external loopback selection? on page 85 0x12 ?test configuration for 10base-t? on page 85 0x29 ?power saving control? on page 86 bit name type description 15 sel_clk125m_dsp mode r/w control bit fo r rgmii interface rx clock delay: 1 = rgmii rx clock delay enable 0 = rgmii rx clock delay disable hw rst. 1 sw rst. retain 14:0 reserved mode ro reserved hw rst. 15?h2e e sw rst. retain bit name type description 15 reserved mode r/w always 0. hw rst. see desc. sw rst. retain 14:9 reserved mode ro reserved hw rst. 0 sw rst. 0
84 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 84 ? august 2011 company confidential 4.3.3 100base-tx test mode select offset: 0x10 ? 8 rgmii_tx_clk_dly mode r/w rgmii tx clock delay control bit: 1 = rgmii tx clock delay enable 0 = rgmii tx clock delay disable. hw rst. 0 sw rst. 0 7:0 reserved mode r/w reserved hw rst. 0 sw rst. 0 bit name type description bit name type description 15:8 reserved mode ro reserved hw rst. 0 sw rst. retain 7 jitter_test mode r/w 100bt jitter test hw rst. 0 sw rst. retain 6 os_test mode r/w 100bt over shoot test hw rst. 0 sw rst. retain 5 dcd_test mode r/w 100bt dcd test hw rst. 0 sw rst. retain 4:0 reserved mode ro reserved hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 85 ? company confidential august 2011 ? 85 4.3.4 hib control and auto-negotiation test register offset: 0x0b (hex) or 11 (decimal) ? 4.3.5 external loopback selection offset: 0x11 (hex) or 17 (decimal) ? 4.3.6 test configuration for 10base-t offset: 0x12 (hex) or 18 (decimal) bit name type description 15 ps_hib_en mode r/w power hibernate control bit; 1: hibernate enable 0: hibernate disable hw rst. 1 sw rst. retain 14:13 reserved mode ro reserved hw rst. 2?h01 sw rst. retain 12 hib_pulse_sw mode r/w reserved hw rst. 1 sw rst. retain 11:7 reserved mode r/w reserved hw rst. 5?h18 sw rst. retain 6:5 reserved mode ro reserved hw rst. 2?b10 sw rst. retain 4:0 reserved mode r/w reserved hw rst. 5?h0 sw rst. retain bit name type description 15:1 reserved mode r/w reserved hw rst. 15?h 3aa9 sw rst. retain 0 ext_lpbk mode r/w 1: enable the phy's ex ternal loopback, namely channel 0<- > channel 1, channel 2 <-> channel 3. hw rst. 0 sw rst. retain
86 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 86 ? august 2011 company confidential 4.3.7 power saving control offset: 0x29 (hex) or 41(decimal) ? bit name type description 15:6 reserved mode ro reserved hw rst. 010011 0000 sw rst. retain 5 test_mode[2] mode ro bit2 of test_mode, used together wi th test_mode[1:0] hw rst. 0 sw rst. retain 4 reserved mode ro reserved hw rst. 0 sw rst. retain 3 rgmii_mode mode ro upon hardware reset, this bit depends on chip_sel and mode_cfg; 1 = select rgmii interface with mac; 0 = select gmii/mii interface with mac. hw rst. 1 sw rst. retain 2 reserved mode r/w reserved hw rst. 1 sw rst. 1 1:0 test_mode[1:0] mode r/w bit 0 and 1 of test _mode, used together with test_mode[2] 001= packet with all ones, 10m hz sine wave, for harmonic test. 010 = pseudo random, for tp _idle/jitter/differential voltage test. 011 = normal link pulse only, 100 = 5mhz sin wave. others: normal mode. hw rst. 0 sw rst. 0 bit name type description 15 top_ps_en mode r/w 1 = top level power saving enable 0 = top level power saving disable hw rst. 0 sw rst. retain 14:0 reserved mode r/w hw rst. 36dd sw rst. retain
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 87 ? company confidential august 2011 ? 87 4.4 mdio interface register mdio interface registers are categorized to two groups: n mmd3 ? mdio manageable device address 3 for pcs n mmd7 ? mdio manageable device address 7 for auto-negotiation table 4-4. mmd3 register summary bit name 0x0 ?pcs control? on page 90 0x1 ?pcs status? on page 90 0x14 ?eee capability? on page 91 0x16 ?eee wake error counter? on page 91 0x8012 ?p1588 control register? on page 92 0x8013 ?p1588 rx_seqid? on page 93 0x8014 ?p1588 rx_sourceport_identity? on page 93 0x8015 ?p1588 rx_sourceport_identity? on page 93 0x8016 ?p1588 rx_sourceport_identity? on page 93 0x8017 ?p1588 rx_sourceport_identity? on page 94 0x8018 ?p1588 rx_sourceport_identity? on page 94 0x8019 ?p1588 rx_time_stamp? on page 94 0x801a ?p1588 rx_time_stamp? on page 94 0x801b ?p1588 rx_time_stamp? on page 95 0x801c ?p1588 rx_time_stamp? on page 95 0x801d ?p1588 rx_time_stamp? on page 95 0x801e ?p1588 rx_frac_nano? on page 95 0x801f ?p1588 rx_frac_nano? on page 96 0x8020 ?p1588 tx_seqid? on page 96 0x8021 ?p1588 tx_sourceport_identity? on page 96 0x8022 ?p1588 tx_sourceport_identity? on page 96 0x8023 ?p1588 tx_sourceport_identity? on page 97 0x8024 ?p1588 tx_sourceport_identity? on page 97 0x8025 ?p1588 tx_sourceport_identity? on page 97 0x8026 ?p1588 tx_timestamp? on page 98 0x8027 ?p1588 tx_timestamp? on page 98 0x8028 ?p1588 tx_time_stamp? on page 98 0x8029 ?p1588 tx_time_stamp? on page 98 0x802a ?p1588 tx_time_stamp? on page 98
88 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 88 ? august 2011 company confidential 0x802b ?p1588 tx_frac_nano? on page 99 0x802c ?p1588 tx_frac_nano? on page 99 0x802d ?p1588 orgin_correction_o? on page 99 0x802e ?p1588 orgin_correction_o? on page 100 0x802f ?p1588 orgin_correction_o? on page 100 0x8030 ?p1588 orgin_correction_o? on page 100 0x8031 ?p1588 ingress_trig_time_o? on page 100 0x8032 ?p1588 ingress_trig_time_o? on page 100 0x8033 ?p1588 ingress_trig_time_o? on page 101 0x8034 ?p1588 ingress_trig_time_o? on page 101 0x8035 ?p1588 tx_latency_o? on page 101 0x8036 ?p1588 inc_value_o? on page 102 0x8037 ?p1588 inc_value_o? on page 102 0x8038 ?p1588 nano_offset_o? on page 102 0x8039 ?p1588 nano_offset_o? on page 102 0x803a ?p1588 sec_offset_o? on page 103 0x803b ?p1588 sec_offset_o? on page 103 0x803c ?p1588 sec_offset_o? on page 103 0x803d ?p1588 real_time_i? on page 103 0x803e ?p1588 real_time_i? on page 103 0x803f ?p1588 real_time_i? on page 104 0x8040 ?p1588 real_time_i? on page 104 0x8041 ?p1588 real_time_i? on page 104 0x8042 ?p1588 real_time_i? on page 104 0x8042 ?p1588 rtc_frac_nano_i? on page 104 0x8043 ?p1588 rtc_frac_nano_i? on page 105 0x804a ?wake-on-lan internal address 1? on page 105 0x804b ?wake-on-lan internal address 2? on page 105 0x804c ?wake-on-lan internal address 3? on page 105 0x805a ?rem_phy_lpbk? on page 106 0x805b ?smarteee control 1? on page 106 0x805c ?smarteee control 2? on page 106 0x805d ?smarteee control 3? on page 107 table 4-4. mmd3 register summary bit name
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 89 ? company confidential august 2011 ? 89 table 4-5. mmd7 register summary bit name 0x0 ?auto-negotiation control 1? on page 107 0x1 ?auto-negotiation status? on page 108 0x16 ?auto-negotiation xnp transmit? on page 108 0x17 ?auto-negotiation xnp transmit1? on page 108 0x18 ?auto-negotiation xnp transmit2? on page 109 0x19 ?auto-negotiation lp xnp ability? on page 109 0x1a ?auto-negotiation lp xnp ability1? on page 109 0x1b ?auto-negotiation lp xnp ability2? on page 109 0x3c ?eee advertisement? on page 110 0x3d ?eee lp advertisement? on page 110 0x8000 ?eee ability auto-negotiation result? on page 111 0x8005 ?sgmii control register 1? on page 111 0x8011 ?sgmii control register 2? on page 112 0x8012 ?sgmii control register 3? on page 112 0x8016 ?clk_25m clock select? on page 112 0x8017 ?1588 clock select? on page 113
90 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 90 ? august 2011 company confidential 4.4.1 pcs control device address = 3 offset: 0x0 (hex) 4.4.2 pcs status device address = 3 offset: 0x1 (hex) bit name description 15 pcs_rst mode r/w reset bit, self clear. when write this bit 1: non-vendor specific registers in mmd3/mmd7 are reset. software reset in mii register0 bit15. hw rst. 0 sw rst. 0 14:11 reserved mode ro always 0. hw rst. 0 sw rst. 0 10 clock_stoppable mod e r/w not implement. hw rst. 0 sw rst. retain 9.0 reserved mode ro always 0. hw rst. 0 sw rst. 0 bit name description 15:12 reserved mode ro always 0. hw rst. 0 sw rst. 0 11 tx lp idle received mode ro when read as 1, it indicates that the transmit pcs has received low power idle signaling one or more times since the register was last read. latch high. hw rst. 0 sw rst. 0 10 rx lp idle received mode ro when read as 1, it indicates that the receive pcs has received low power idle signaling one or more times since the register was last read. latch high. hw rst. 0 sw rst. 0 9 tx lp idle indication mode ro when read as 1, it indicates that the transmit pcs is currently receiving low power idle signals. hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 91 ? company confidential august 2011 ? 91 4.4.3 eee capability device address = 3 offset: 0x14 (hex) 4.4.4 eee wake error counter device address = 3 offset: 0x16 (hex) 8 rx lp idle indication mode ro when read as 1, it indicates that the receive pcs is currently receiving low power idle signals. hw rst. 0 sw rst. 0 7:0 reserved mode ro always 0. hw rst. 0 sw rst. 0 bit name description bit name description 15:3 reserved mode ro always 0. hw rst. 0 sw rst. 0 2 1000bt eee mode ro eee is supported for 1000 base-t. hw rst. 1 sw rst. 1 1 100bt eee mode ro eee is supported for 100 base-t. hw rst. 1 sw rst. 1 0 reserved mode ro always 0. hw rst. 0 sw rst. 0 bit name description 15: eee wake error counter mode ro count wake time faults where the phy fails to complete its normal wake sequence within the time required for the specific phy type. this counter is clear after read , and hold at all ones in the case of overflow. hw rst. 0 sw rst. 0
92 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 92 ? august 2011 company confidential 4.4.5 p1588 control register device address = 3 offset: 0x8012 (hex) bit name description 15:8 reserved mode ro reserved hw rst. 0 sw rst. 0 7 rtc_clk_select mode r/w select rtc_cl k for ieee1588 real time counter. 0: local free running clock. 1: synce recovered clock. hw rst. 1?b0 sw rst. retain 6 reserved mode r/w reserved hw rst. 1?b0 sw rst. retain 5 wol_en mode r/w 0: disable wake-on-lan function. 1: enable wake-on-lan funciton. hw rst. 1?b1 sw rst. retian 4 attach_en mode r/w 0: disable attaching ti mestamp at the end of received ptp messages. 1: enable attaching timestamp at the end of received ptp messages. hw rst. 1?b1 sw rst. retain 3 bypass mode r/w 0: ieee1588v2 normal operation. 1: bypass ieee1588v2 functions. hw rst. 1?b1 sw rst. retain 2:1 clock_mode mode r/w 00: ordina ry/boundary two-step clock. 01: ordinary/boundary one-step clock. 10: transparent two-step clock. 11: transparent one-step clock. hw rst. 2?b00 sw rst. retain 0 reserved mode r/w reserved hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 93 ? company confidential august 2011 ? 93 4.4.6 p1588 rx_seqid device address = 3 offset: 0x8013 (hex) 4.4.7 p1588 rx_sourceport_identity device address = 3 offset: 0x8014 (hex) 4.4.8 p1588 rx_sourceport_identity device address = 3 offset: 0x8015 (hex) 4.4.9 p1588 rx_sourceport_identity device address = 3 offset: 0x8016 (hex) bit name description 15:0 rx_seqid mode ro sequenceid of the mose recently received ieee1588v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 rx_sourceport identity[79:64] mode ro the most significant 16 bits ([79:64]) of sourceportidentity of the most recently rece ived ieee1588v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 rx_sourceport identity[63:48] mode ro bits [63:48] of sourceportidentity of the most recently received ieee1588v 2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 rx_sourceport identity[47:32] mode ro bits [47:32] of sourceportidentity of the most recently received ieee1588v 2 event message. hw rst. 0 sw rst. 0
94 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 94 ? august 2011 company confidential 4.4.10 p1588 rx_sourceport_identity device address = 3 offset: 0x8017 (hex) 4.4.11 p1588 rx_sourceport_identity device address = 3 offset: 0x8018 (hex) 4.4.12 p1588 rx_time_stamp device address = 3 offset: 0x8019 (hex) 4.4.13 p1588 rx_time_stamp device address = 3 offset: 0x801a (hex) bit name description 15:0 rx_sourceport identity[31:16] mode ro bits [31:16] of sourceportidentity of the most recently received ieee1588v 2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 rx_sourceport identity[15:0] mode ro bits [15:0] of sourceportid entity of the most recently received ieee1588v 2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 rx_time_ stamp[79:64] mode ro the most significant 16 [79:64] bits of rx timestamp for the most recently received ieee1588v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 rx_time_ stamp[63:48] mode ro bits [63:48] of rx timestamp for the most recently received ieee1588v2 event message. hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 95 ? company confidential august 2011 ? 95 4.4.14 p1588 rx_time_stamp device address = 3 offset: 0x801b (hex) 4.4.15 p1588 rx_time_stamp device address = 3 offset: 0x801c (hex) 4.4.16 p1588 rx_time_stamp device address = 3 offset: 0x801d (hex) 4.4.17 p1588 rx_frac_nano device address = 3 offset: 0x801e (hex) bit name description 15:0 rx_time_ stamp[47:32] mode ro bits [47:32] of rx timestamp for the most recently received ieee1588v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 rx_time_ stamp[31:16] mode ro bits [31:16] of rx timestamp for the most recently received ieee1588v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 rx_time_ stamp[15:0] mode ro bits [15:0] of rx timestamp for the most recently received ieee1588v2 event message. hw rst. 0 sw rst. 0 bit name description 15:12 rx_messagetype mode ro messagetype of the most recently received ieee1588v2 event message. hw rst. 0 sw rst. 0 11:0 rx_frac_nano[19:8] mode ro bits [19:8] of fr actional nanoseconds fi eld of rx timestamp for the most recently rece ived ieee1588v2 event message. hw rst. 0 sw rst. 0
96 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 96 ? august 2011 company confidential 4.4.18 p1588 rx_frac_nano device address = 3 offset: 0x801f (hex) 4.4.19 p1588 tx_seqid device address = 3 offset: 0x8020 (hex) 4.4.20 p1588 tx_sourceport_identity device address = 3 offset: 0x8021 (hex) 4.4.21 p1588 tx_sourceport_identity device address = 3 offset: 0x8021 (hex) bit name description 15:8 reserved mode ro hw rst. 0 sw rst. 0 7:0 rx_frac_nano[7:0] mode ro bits [7:0] of frac tional nanoseconds field of rx timestamp for the most recently rece ived ieee1588v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 tx_seqid mode ro sequenceid of the mo se recently transmitted ieee1588v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 tx_sourceport identity[79:64] mode ro the most significant 16 bits ([79:64]) of sourceportidentity of the most recently transmitted ieee1588v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 tx_sourceport identity[79:64] mode ro the most significant 16 bits ([79:64]) of sourceportidentity of the most recently transmitted ieee1588v2 event message. hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 97 ? company confidential august 2011 ? 97 4.4.22 p1588 tx_sourceport_identity device address = 3 offset: 0x8022 (hex) 4.4.23 p1588 tx_sourceport_identity device address = 3 offset: 0x8023 (hex) 4.4.24 p1588 tx_sourceport_identity device address = 3 offset: 0x8024 (hex) 4.4.25 p1588 tx_sourceport_identity device address = 3 offset: 0x8025 (hex) bit name description 15:0 tx_sourceport identity[63:48] mode ro bits [63:48] of sourceportidentity of the most recently transmitted ieee15 88v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 tx_sourceport identity[47:32] mode ro bits [47:32] of sourceportidentity of the most recently transmitted ieee15 88v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 tx_sourceport identity[31:16] mode ro bits [31:16] of sourceportidentity of the most recently transmitted ieee15 88v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 tx_sourceport identity[15:0] mode ro bits [15:0] of sourceportid entity of the most recently transmitted ieee15 88v2 event message. hw rst. 0 sw rst. 0
98 ? AR8031 integrated 10/100/1000 mbps ethe rnet transceiver atheros communications, inc. ? 98 ? august 2011 company confidential 4.4.26 p1588 tx_timestamp device address = 3 offset: 0x8026 (hex) 4.4.27 p1588 tx_timestamp device address = 3 offset: 0x8027 (hex) 4.4.28 p1588 tx_time_stamp device address = 3 offset: 0x 8028(hex) 4.4.29 p1588 tx_time_stamp device address = 3 offset: 0x8029 (hex) 4.4.30 p1588 tx_time_stamp device address = 3 offset: 0x802a(hex) bit name description 15:0 tx_time_ stamp[79:64] mode ro the most significant 16 [79:64 ] bits of tx timestamp for the most recently transmitte d ieee1588v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 tx_time_ stamp[63:48] mode ro bits [63:48] of tx timestamp for the most recently transmitted ieee15 88v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 tx_time_ stamp[47:32] mode ro bits [47:32] of tx timestamp for the most recently transmitted ieee15 88v2 event message. hw rst. 0 sw rst. 0 bit name description 15:0 tx_time_ stamp[31:16] mode ro bits [31:16] of tx timest amp for the most recently transmitted ieee1588v2 event message. hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 99 ? company confidential august 2011 ? 99 4.4.31 p1588 tx_frac_nano device address = 3 offset: 0x802b (hex) 4.4.32 p1588 tx_frac_nano device address = 3 offset: 0x802b (hex) 4.4.33 p1588 orgin_correction_o device address = 3 offset: 0x802d(hex) bit name description 15:0 tx_time_ stamp[15:0] mode ro bits [15:0] of tx timestamp for the most recently transmitted ieee15 88v2 event message. hw rst. 0 sw rst. 0 bit name description 15:12 tx_messagetype mode ro messagetype of the most recently transmitted ieee1588v2 event message. hw rst. 0 sw rst. 0 11:0 tx_frac_nano[19:8] mode ro bits [19:8] of fr actional nanoseconds field of tx timestamp for the most recently transmitted ieee1588v2 event message hw rst. 0 sw rst. 0 bit name description 15:12 tx_messagetype mode ro messagetype of the most recently transmitted ieee1588v2 event message. hw rst. 0 sw rst. 0 11:0 tx_frac_nano[19:8] mode ro bits [19:8] of fr actional nanoseconds field of tx timestamp for the most recently transmitted ieee1588v2 event message hw rst. 0 sw rst. 0 bit name description 15:0 origin_ correction_o[63:48] mode ro bits [63:48] of original co rrectionfield of the ieee1588v2 event message to be transmitted. this is used in one-step clock mode, provide information for hardware operation. hw rst. 0 sw rst. 0
100 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 100 ? august 2011 company confidential 4.4.34 p1588 orgin_correction_o device address = 3 offset: 0x802e (hex) 4.4.35 p1588 orgin_correction_o device address = 3 offset: 0x802f (hex) 4.4.36 p1588 orgin_correction_o device address = 3 offset: 0x8030 (hex) 4.4.37 p1588 ingress_trig_time_o device address = 3 offset: 0x8031 (hex) 4.4.38 p1588 ingress_trig_time_o device address = 3 offset: 0x8032 (hex) bit name description 15:0 origin_ correction_o[47:32] mode ro bits [47:32] of original co rrectionfield of the ieee1588v2 event message to be transmitted. this is used in one-step clock mode, provide information for hardware operation. hw rst. 0 sw rst. 0 bit name description 15:0 origin_ correction_o[31:16] mode ro bits [31:16] of original co rrectionfield of the ieee1588v2 event message to be transmitted. this is used in one-step clock mode, provide information for hardware operation. hw rst. 0 sw rst. 0 bit name description 15:0 origin_ correction_o[15:0] mode ro bits [15:0] of original co rrectionfield of the ieee1588v2 event message to be transmitted. this is used in one-step clock mode, provide information for hardware operation. hw rst. 0 sw rst. 0 bit name description 15:0 ingress_trig_ time_o[51:36] mode ro bits [31:16] of nanoseconds field of rx timestamp of associate received event message for the ieee1588v2 event message to be transmitted. this is used in one-step clock mode, provide information for hardware calculation. hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 101 ? company confidential august 2011 ? 101 4.4.39 p1588 ingress_trig_time_o device address = 3 offset: 0x8033 (hex) 4.4.40 p1588 ingress_trig_time_o device address = 3 offset: 0x8034 (hex) 4.4.41 p1588 tx_latency_o device address = 3 offset: 0x8035(hex) bit name description 15:0 ingress_trig_ time_o[51:36] mode ro bits [31:16] of nanoseconds field of rx timestamp of associate received event message for the ieee1588v2 event message to be transmitted. this is used in one-step clock mode, provide information for hardware calculation. hw rst. 0 sw rst. 0 bit name description 15:0 ingress_trig_ time_o[19:4] mode ro bits [19:4] of fractional na noseconds field of rx timestamp of associate received event message for the ieee1588v2 event message to be transmitted. this is used in one-step clock mode, provide information for hardware calculation. hw rst. 0 sw rst. 0 bit name description 15:12 reserved mode ro hw rst. 0 sw rst. 0 11:0 ingress_trig _time_o[3:0] mode ro bits [3:0] of fractional na noseconds field of rx timestamp of associate received event message for the ieee1588v2 event message to be transmitted. this is used in one-step clock mode, provide information for hardware calculation. hw rst. 0 sw rst. retain bit name description 15:0 tx_latency_o mode ro transmi ssion latency from tx timestamp reference plan to the physical media, unit in nanoseconds. this is used in one-step clock mode, provide information for hardware calculation. hw rst. 0 sw rst. retain
102 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 102 ? august 2011 company confidential 4.4.42 p1588 inc_value_o device address = 3 offset: 0x8036 (hex) 4.4.43 p1588 inc_value_o device address = 3 offset: 0x8037 (hex) 4.4.44 p1588 nano_offset_o device address = 3 offset: 0x8038 (hex) 4.4.45 p1588 nano_offset_o device address = 3 offset: 0x8039 (hex) bit name description 15:0 inc_value_o[25:10] mode ro bit [25:10] of increment value for the ieee1588v2 rtc counter. software can adjust this valu e, thus adjust tick rate. bits [25:20] is nanosecond part, [19:0] is fractional nanoseconds. hw rst. 0 sw rst. retain bit name description 15:10 reserved mode ro hw rst. 0 sw rst. 0 9:0 inc_vaule_o[9:0] mode ro bit [9:0] of increment value for the ieee1588v2 rtc counter. software can adjust this valu e, thus adjust tick rate. bits [25:20] is nanosecond part, [19:0] is fractional nanoseconds. hw rst. 0 sw rst. 0 bit name description 15:0 nano_offset_o[31:16 ] mode ro bits [31:16] of nanoseconds field of time difference between master and slave. hw rst. 0 sw rst. retain bit name description 15:0 nano_offset_o[15:0] mode ro bits [15:0] of na noseconds field of time difference between master and slave. hw rst. 0 sw rst. retain
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 103 ? company confidential august 2011 ? 103 4.4.46 p1588 sec_offset_o device address = 3 offset: 0x803a (hex) 4.4.47 p1588 sec_offset_o device address = 3 offset: 0x803b (hex) 4.4.48 p1588 sec_offset_o device address = 3 offset: 0x803c (hex) 4.4.49 p1588 real_time_i device address = 3 offset: 0x803d (hex) 4.4.50 p1588 real_time_i device address = 3 offset: 0x803e (hex) bit name description 15:0 sec_offset_o[47:32] mode ro bits [47:32] of seconds field of time difference between master and slave. hw rst. 0 sw rst. retain bit name description 15:0 sec_offset_o[31:16] mode ro bits [31:16] of seconds field of time difference between master and slave. hw rst. 0 sw rst. retain bit name description 15:0 sec_offset_o[15:0] mode ro bits [15:0] of se conds field of time difference between master and slave. hw rst. 0 sw rst. retain bit name description 15:0 real_time_i[79:64] mode ro bits [79:64] of current rtc counter implemented for ieee1588v2. bits [79: 32] corresponding to seconds field, bits [31:0] corresponding to nanoseconds field. hw rst. 0 sw rst. retain
104 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 104 ? august 2011 company confidential 4.4.51 p1588 real_time_i device address = 3 offset: 0x803f (hex) 4.4.52 p1588 real_time_i device address = 3 offset: 0x8040 (hex) 4.4.53 p1588 real_time_i device address = 3 offset: 0x8041 (hex) 4.4.54 p1588 rtc_frac_nano_i device address = 3 offset: 0x8042 (hex) bit name description 15:0 real_time_i[63:48] mode ro bits [63:48] of current rtc counter implemented for ieee1588v2. bits [79: 32] corresponding to seconds field, bits [31:0] corresponding to nanoseconds field. hw rst. 0 sw rst. retain bit name description 15:0 real_time_i[47:32] mode ro bits [47:32] of current rtc counter implemented for ieee1588v2. bits [79: 32] corresponding to seconds field. bits [31:0] corresponding to nanoseconds field. hw rst. 0 sw rst. 0 bit name description 15:0 real_time_i[31:16] mode ro bits [31:16] of current rtc counter implemented for ieee1588v2. bits [79: 32] corresponding to seconds field. bits [31:0] corresponding to nanoseconds field. hw rst. 0 sw rst. 0 bit name description 15:0 real_time_i[15:0] mode ro bits [15:0] of current rtc counter implemented for ieee1588v2. bits [79: 32] corresponding to seconds field. bits [31:0] corresponding to nanoseconds field. hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 105 ? company confidential august 2011 ? 105 4.4.55 p1588 rtc_frac_nano_i device address = 3 offset: 0x8043 (hex) 4.4.56 wake-on-lan internal address 1 device address = 3 offset: 0x804a (hex) 4.4.57 wake-on-lan internal address 2 device address = 3 offset: 0x804b (hex) 4.4.58 wake-on-lan internal address 3 bit name description 15:0 rtc_frac_nano_i[19: 4] mode ro bits [19:4] of fractional nanoseconds field of current rtc counter implemented for ieee1588v2. hw rst. 0 sw rst. 0 bit name description 15:12 reserved mode ro hw rst. 0 sw rst. 0 11:0 rtc_frac_nano_i[3:0] mode ro bits [3:0] of fr actional nanoseconds field of current rtc counter implemented for ieee1588v2 hw rst. 0 sw rst. 0 bit name description 15:0 loc_mac_ addr_o[47:32] mode r/w bits [47:32] of internal address, used in wake-on-lan. hw rst. 0 sw rst. retain bit name description 15:0 loc_mac_ addr_o[31:16] mode r/w bits [31:16] of internal address, used in wake-on-lan. hw rst. 0 sw rst. retain
106 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 106 ? august 2011 company confidential device address = 3 offset: 0x804c (hex) 4.4.59 rem_phy_lpbk device address = 3 offset: 0x805a (hex) 4.4.60 smarteee control 1 device address = 3 offset: 0x805b (hex) 4.4.61 smarteee control 2 device address = 3 offset: 0x805c (hex) bit name description 15:0 loc_mac_ addr_o[15:0] mode r/w bits [15:0] of internal address, used in wake-on-lan. hw rst. 0 sw rst. retain bit name description 15:1 reserved mode ro reserved hw rst. 0 sw rst. 0 0 rem_phy_lpbk mode r/w loop back received data packets to link partner hw rst. 0 sw rst. retain bit name description 15:8 lpi_wt mode r/w 1000 base-t tw timer. buffered data is sent after time out. lsb vs time: 1 s default value: 17 s hw rst. 0x11 sw rst. retain 7:0 lpi_wt mode r/w 100 base-t tw timer. buff ered data is sent after time out. lsb vs time: 1 s default value: 17 s hw rst. 0x17 sw rst. retain
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 107 ? company confidential august 2011 ? 107 4.4.62 smarteee control 3 device address = 3 offset: 0x805d (hex) 4.4.63 auto-negotiation control 1 device address = 7 offset: 0x0 (hex) bit name description 15:0 lpi_timer mode r/w the lpi_ timer is for action when no data is being transmitted. when timed ou t, phy enters lpi mode. lsb vs time: 163.84 s default value: 335.544 ms hw rst. 0x800 sw rst. retain bit name description 15:14 reserved mode ro reserved hw rst. 0 sw rst. 0 13:12 lpi_tx_delay_sel mode r/w se lect ipg length inserted between packets (for debug use). hw rst. 01 sw rst. retain 11:9 reserved mode ro reserved hw rst. 0 sw rst. 0 8 lpi_en mode r/w enables or disables smarteee 1 = enable 0 = disable hw rst. 1 sw rst. retain 7:0 lpi_timer mode r/w the lpi_timer coun ter to see when no data is being transmitted. when lpi_timer times out, phy enters lpi mode. hw rst. 0 sw rst. retain bit name description 15 an_rst mode r/w reset bit, self clear. when write this bit 1: 1, reset the registers (not vender specific) in mmd3/ mmd7. 2, cause software reset in mii register0 bit15. hw rst. 0 sw rst. 0
108 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 108 ? august 2011 company confidential 4.4.64 auto-negotiation status device address = 7 offset: 0x1 (hex) 4.4.65 auto-negotiation xnp transmit device address = 7 offset: 0x16 (hex) 4.4.66 auto-negotiation xnp transmit1 device address = 7 14 reserved mode ro always 0. hw rst. 0 sw rst. 0 13 xnp_ctrl mode r/w if mii register4 bit12 is set to 0, setting of this bit shall have no effect. 1 = local device intends to enable the exchange of extended next page; 0 = local device does not intend to enable the exchange of extended next page; hw rst. 1?b1 sw rst. retain 12:0 reserved mode ro always 0. hw rst. 0 sw rst. 0 bit name description bit name description 15:8 reserved mode ro hw rst. 0 sw rst. 0 7 xnp_status mode ro 1 = both local device and link partner have indicated support for extended next page; 0 = extended next page shall not be used. hw rst. 0 sw rst. 0 6:0 reserved mode ro hw rst. 0 sw rst. 0 bit name description 15:0 xnp_22 mode r/w a write to this re gister set mr_next_page_loaded. hw rst. 15?h0 sw rst. retain
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 109 ? company confidential august 2011 ? 109 offset: 0x17 (hex) 4.4.67 auto-negotiation xnp transmit2 device address = 7 offset: 0x18 (hex) 4.4.68 auto-negotiation lp xnp ability device address = 7 offset: 0x19 (hex) 4.4.69 auto-negotiation lp xnp ability1 device address = 7 offset: 0x1a (hex) 4.4.70 auto-negotiation lp xnp ability2 device address = 7 offset: 0x1b (hex) bit name description 15:0 xnp_23 mode r/w hw rst. 15?h0 sw rst. retain bit name description 15:0 xnp_24 mode r/w hw rst. 15?h0 sw rst. retain bit name description 15:0 lp_xnp_1 mode r/w hw rst. 15?h0 sw rst. 15?h0 bit name description 15:0 lp_xnp_2 mode r/w latched when lp_xnp_1 is read hw rst. 15?h0 sw rst. 15?h0
110 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 110 ? august 2011 company confidential 4.4.71 eee advertisement device address = 7 offset: 0x3c (hex) 4.4.72 eee lp advertisement device address = 7 offset: 0x3d (hex) bit name description 15:0 lp_xnp_3 mode r/w latched when lp_xnp_1 is read hw rst. 15?h0 sw rst. 15?h0 bit name description 15:3 reserved mode ro always 0. hw rst. 0 sw rst. 0 2 eee_1000bt mode r/w if local device supports eee operation for 1000bt, and eee operation is desired, this bit shall be set to 1. hw rst. 1?b1 sw rst. retain 1 eee_100bt mode r/w if local device suppo rts eee operation for 100bt, and eee operation is desired, th is bit shall be set to 1. hw rst. 1?b1 sw rst. retain 0 reserved mode ro always 0. hw rst. 0 sw rst. 0 bit name description 15:3 reserved mode ro always 0. hw rst. 0 sw rst. 0 2 eee_1000bt mode ro 1 = link partner supports eee operation for 1000bt, and eee operation is desired; 0 = link partner does not support eee operation for 1000bt, or eee operation is not desired. hw rst. 0 sw rst. 0 1 eee_100bt mode ro 1 = link partner supports eee operation for 100bt, and eee operation is desired; 0 = link partner does not suppo rt eee operation for 100bt, or eee operation is not desired. hw rst. 0 sw rst. 0
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 111 ? company confidential august 2011 ? 111 4.4.73 eee ability auto-negotiation result device address = 7 offset: 0x8000 (hex) 4.4.74 sgmii control register 1 device address = 7 offset: 0x8005 (hex) 0 reserved mode ro always 0. hw rst. 0 sw rst. 0 bit name description bit name description 15:3 reserved mode ro always 0. hw rst. 0 sw rst. 0 2 eee_1000bt_en mode ro 1 = 1000base-t 802.3az enabled. both sides support eee operation for 1000base-t and eee operation is preferred. 0 = 1000base-t 802.3az disabled. either side does not support eee operation for 1000base-t or eee operation is not preferred. hw rst. 0 sw rst. 0 1 eee_100bt_en mode ro 1 = 100base-t 802.3az enabled. both sides support eee operation for 100base-t and eee operation is preferred. 0 = 100base-t 802.3az disabled . either side does not support eee operation for 100base-t or eee operation is not preferred. hw rst. 0 sw rst. 0 0 reserved mode ro always 0. hw rst. 0 sw rst. 0 bit name description 15 serdes hibernation control mode r/w 1 = enable hibernation 0 = disable hibernation hw rst. 1 sw rst. retain 14:0 reserved mode ro hw rst. 0x20c6 sw rst. 0x20c6
112 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 112 ? august 2011 company confidential 4.4.75 sgmii control register 2 device address = 7 offset: 0x8011 (hex) 4.4.76 sgmii control register 3 device address = 7 offset: 0x8012 (hex) 4.4.77 clk_25m clock select device address = 7 offset: 0x8016 (hex) bit name description 15:13 sgmii_txdr_ctrl mode r/w drive output vdiff, peak to peak. 001 = 600 mv 010 = 700 mv 011 = 800 mv 100 = 900 mv others are reserved. hw rst. 001 sw rst. retain 12:0 reserved mode hw rst. sw rst. bit name description 15:2 reserved mode ro hw rst. 0x20f1 sw rst. 0x20f1 1:0 rf_bx_sel mode r/w remote fault in 1000base-x. 00 = controlled by regist er and internal state 11= controlled by register only others = reserved hw rst. 00 sw rst. retain bit name description 15:5 reserved mode hw rst. sw rst.
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 113 ? company confidential august 2011 ? 113 4.4.78 1588 clock select device address = 7 offset: 0x8017 (hex) 4:2 select_clk25m mode r/w clk_25m output clock select bits. 000 = 25 mhz from crystal xout pad 001 = 25 mhz divided down from dsp 1g clock 010 = 50 mhz from local pll source 011 = 50 mhz from dsp source 100 = 62.5 mhz from local pll source 101 = 62.5 mhz from dsp source 110 = 125 mhz from local pll source 111 = 125 mhz from dsp source note: if synchronous ethern et works, dsp clock is recovered from line side; if not, dsp clock smooth changes to local clock. note: clk_25m output 25 mhz cl ock from local crystal by default. when clk_25 is config ured to output 50, 62.5 or 125 mhz clock, the output will be reset to default 25 mhz at hardware reset. hw rst. sw rst. 1:0 reserved mode hw rst. sw rst. bit name description bit name description 15:12 reserved mode ro hw rst. 1110 sw rst. 1110 11 en_iso_50m mode r/w 0 = use internal 1588 rtc clock 1 = user external 1588 rtc clock hw rst. 0 sw rst. retain 10:0 reserved mode ro hw rst. 01010000000 sw rst. 01010000000
114 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 114 ? august 2011 company confidential
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 115 ? company confidential august 2011 ? 115 5. package dimensions the AR8031 is packaged in a 48-pin 6 x 6 mm qfn package. the pa ckage drawings and dimensions are provided in figure 5-1 and table 5-1 . figure 5-1. package views
116 ? AR8031 integrated 10/100/1000 mbps ethern et transceiver atheros communications, inc. ? 116 ? august 2011 company confidential table 5-1. package dimensions dimension label min nom max unit a 0.70 0.75 0.80 mm a1 ? 0.01 0.05 mm b 0.15 0.20 0.25 mm c 0.18 0.20 0.23 mm d 5.90 6.00 6.10 mm d2 3.70 3.80 3.90 mm e 0.35 0.40 0.45 mm ne 4.35 4.40 4.45 mm nd 4.35 4.40 4.45 mm e 5.90 6.00 6.10 mm e2 3.70 3.80 3.90 mm k0.20??mm l 0.35 0.40 0.45 mm h 0.30 0.35 0.40 mm
atheros communications, inc. AR8031 integrated 10/100/1000 mbps ethernet transceiver ? 117 ? company confidential august 2011 ? 117 6. ordering information 7. topside marking table 6-1. AR8031 ordering information ordering number version default ordering unit AR8031-al1a commercial tray pack AR8031-al1a-r commercial tape and reel AR8031-al1b industrial tray pack AR8031-al1b-r industrial tape and reel table 7-1. AR8031 marking ordering number marking AR8031-al1a AR8031-al1a AR8031-al1b AR8031-al1b figure 7-1. topside markings AR8031-al1b AR8031-al1a
company confidential subject to change without notice atheros communications, incorporated 1700 technology drive san jose, ca 95110 tel: 408.773.5200 fax: 408.773.9940 www.atheros.com the information in this document has been ca refully reviewed and is believed to be accurate. nonetheless, this document is subj ect to change without notice. atheros assumes no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update or to keep current the contained information, or to notify a person or or ganization of any updates. athero s reserves the right to make changes, at any time, to improve reliability, function or design and to attempt to supply the best product po ssible. mkg-16649 rev. 1.0

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